HI-3210
APPLICATION OVERVIEW
The HI-3210 is a flexible device for managing ARINC 429
communications and data storage in many avionics
applications. The device architecture centers around a
32K x 8 static RAM used for data storage, data filtering
tables and table-driven transmission schedulers. Once
configured, the device can operate autonomously without
a host CPU, negating the need for software development
or DO-178 certification. Configuration data may be
uploaded into the device from an external EEPROM,
following system reset.
The HI-3210 includes four independent ARINC 429
transmit channels. Transmission may be controlled
entirely by an external CPU, or autonomously by
programming one or more of the four on-chip ARINC 429
transmit schedulers. These allow periodic transmission
to occur without CPU. Source data for transmission may
be selected from RAM based tables of constants and / or
from the received channel data. Powerful options exist for
constructing ARINC 429 labels as well as controlling their
timing and conditional transmission.
The device supports up to eight ARINC 429 receive
channels. Received data is stored in on-chip RAM
organized by channel number and label. The data table
continually updates as new labels arrive. Programmable
interrupts and filters alert the host subsystem to labels of
interest.
Even when running under the control of schedulers, the
host CPU may insert new labels for transmission at will.
The following examples show five possible configurations
of how the HI-3210 may be used:
Each ARINC 429 receive channel also includes a 32
message deep FIFO allowing selected label data to be
queued for subsequent host access.
Example 1. ARINC 429 Data reception using on-chip RAM
Channel 7, Label FF
“
“
“
RECEIVER 7
Channel 7, Label 01
Channel 7, Label 00
Channel 6, Label FF
“
“
“
RECEIVER 6
Channel 6, Label 01
Channel 6, Label 00
Channel 5, Label FF
“
“
“
RECEIVER 5
AINT
ARINC 429
RECEIVE
Channel 5, Label 01
8 x ARINC 429
Receive Buses
Channel 5, Label 00
INTERRUPT
TABLE
AACK
Channel 4, Label FF
“
Host CPU
“
“
RECEIVER 4
RECEIVER 3
HCSB
Channel 4, Label 01
Channel 4, Label 00
HSCLK
HMOSI
HMISO
SPI
Channel 3, Label FF
“
“
“
Channel 3, Label 01
Channel 3, Label 00
Channel 2, Label FF
“
“
“
RECEIVER 2
RECEIVER 1
Channel 2, Label 01
Channel 2, Label 00
Channel 1, Label FF
“
“
“
Channel 1, Label 01
Channel 1, Label 00
Channel 0, Label FF
“
“
“
RECEIVER 0
Channel 0, Label 01
Channel 0, Label 00
8K x 8 RAM
HI-3210
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
