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HI-3210PQI 参数 Datasheet PDF下载

HI-3210PQI图片预览
型号: HI-3210PQI
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429数据管理引擎/八通道接收器/发射器四 [ARINC 429 DATA MANAGEMENT ENGINE / Octal Receiver / Quad Transmitter]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路
文件页数/大小: 42 页 / 159 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3210  
ARINC 429 TRANSMIT OPERATION  
The HI-3210 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers  
such as the Holt HI-8596. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction,  
or be generated automatically using the four ARINC 429 message schedulers.  
ARINC 429 Transmit Channel Configuration  
Each of the four available ARINC 429 Transmit channels is configured using its own register. Register address 0x8018  
controls ARINC 429 Transmit channel #0, register address 0x8019 controls channel #1 and so on. The ATXCn  
registers may be written or read at any time.  
X
2
X
1
X
ARINC 429 TX CONTROL REGISTER 0 - 3  
(Address 0x8018 - 0x801B)  
7
6
5
4
3
0
LSB  
MSB  
Bit Name  
R/W Default Description  
7
RUN / STOP  
R/W  
0
When zero, transmission from this ARINC 429 transmit channel is suspended after the  
currently transmitting label is sent. When this bit is taken high, transmission starts at the  
beginning of the descriptor table for this channel.  
6
5
4
3
HI / LO  
R/W  
0
0
0
0
Selects the transmission rate for the ARINC 429 transmit channel. A “0” selects high-speed  
(100Kb/s) and a “1” selects low-speed (12.5Kb/s).  
PARITY/ DATA R/W  
When this bit is a one, the 32nd transmitted ARINC bit is overwritten with a parity flag. When  
this bit is a zero, all 32-bits are transmitted as data.  
EVEN / ODD  
SKIP  
R/W  
R/W  
When PARITY / DATAis a “1”, this bit defines whether th 32nd transmitted bit is set for Even or  
Odd Parity.A1” selects even parity and a “0” selects odd parity.  
When set a “1’ instructs the transmit sequencer to wait for the next Repetition Rate Counter  
rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the  
cycle following completion of the prior cycle.  
2
1
0
-
-
-
R/W  
R/W  
R/W  
0
0
0
Not Used  
Not Used  
Not Used  
HOLT INTEGRATED CIRCUITS  
20  
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