HI-3210
ARINC 429 Received Data FIFO Status Registers
AFNE0
FIFO NOT EMPTY REGISTER
(Address 0x802B)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
AFNE7
AFNE6
AFNE5
AFNE4
AFNE3
AFNE2
AFNE1
AFNE0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
This bit is set to “1” if FIFO #7 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #6 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #5 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #4 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #3 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #2 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #1 contains at least oneARINC 429 message
This bit is set to “1” if FIFO #0 contains at least oneARINC 429 message
AFTF0
FIFO THRESHOLD REGISTER
(Address 0x802A)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
AFTF7
AFTF6
AFTF5
AFTF4
AFTF3
AFTF2
AFTF1
AFTF0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
This bit is set to “1” if FIFO #7 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #6 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #5 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #4 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #3 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #2 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #1 contains > threshold number ofARINC 429 messages
This bit is set to “1” if FIFO #0 contains > threshold number ofARINC 429 messages
AFFF0
FIFO FULL REGISTER
(Address 0x8029)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
5
4
3
2
1
0
AFFF7
AFFF6
AFFF5
AFFF4
AFFF3
AFFF2
AFFF1
AFFF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
This bit is set to “1” if FIFO #7 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #6 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #5 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #4 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #3 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #2 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #1 contains 32ARINC 429 messages
This bit is set to “1” if FIFO #0 contains 32ARINC 429 messages
HOLT INTEGRATED CIRCUITS
16
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
