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HI-3210PCM 参数 Datasheet PDF下载

HI-3210PCM图片预览
型号: HI-3210PCM
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429数据管理引擎/八通道接收器/发射器四 [ARINC 429 DATA MANAGEMENT ENGINE / Octal Receiver / Quad Transmitter]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路
文件页数/大小: 42 页 / 159 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-3210
ARINC 429 Received Data Management
The HI-3210 supports eight ARINC 429 receive buses
using on-chip receivers to handle the protocol validation.
The eight ARINC 429 RX Control Registers, ARXC0 - 7,
define the characteristics of each receive channel.
The ARINC 429 receive function of the HI-3210 is acti-
vated by setting the A429RX bit in the Master Control
Register.
When an ARINC 429 message is received by the HI-3210
on any bus, it is checked for protocol compliance. Mes-
sages with incorrect encoding are rejected.
The HI-3210 contains an 8K byte memory for storing
ARINC 429 received data. The memory is organized by
channel number and ARINC 429 label value. Four bytes of
memory are dedicated to each channel / label to store the
32-word ARINC 429 message.
A look-up table is used to enable an interrupt on receipt of a
new ARINC 429 message. Look-up table bit positions pre-
loaded with a “1” will cause an Interrupt to be generated.
When a message is received that triggers an Interrupt, that
channel’s Interrupt bit is set in the ARINC 429 Receive
Pending Interrupt Register. If this bit is unmasked in the
ARINC 429 Receive Interrupt Mask Register, the AINT
output pin is asserted. The label number of the ARINC 429
message causing the interrupt is loaded into that chan-
nel’s ARINC 429 Receive Interrupt Address Register
(AIAR0 - AIAR7).
Because the ARINC Receive Memory is organized by
label value, it is not necessary to store the received label
value (first eight bits of the ARINC message) in the
memory. Instead, the first byte is used to store a status
byte.
The six active bits of the status byte are set to “1” when a
new ARINC word is stored in the memory. These bits flag
the ARINC word as new when the location is interrogated
by the host CPU or any of the four ARINC 429 transmit
schedulers.
ARINC 429 Received Data Memory Organization
0x1FFF
0x1FFC
Block 2048
Channel 7, Label FF
0x000B
0x0008
0x0007
Block 3
Channel 0, Label 02
Block 2
Channel 0, Label 01
0x0003
0x0002
0x0001
0x0000
Etc.
ARINC data byte 4
ARINC data byte 3
ARINC data byte 2
Status Byte
0x0004
0x0003
Block 1
Channel 0, Label 00
0x0000
HOLT INTEGRATED CIRCUITS
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