HI-3200, HI-3201
CANBTR1 cont.
Bit
Name
R/W Default Description
5:0 TSEG1-3:0 R/W
0
Time segment 1 length. Tseg1 = Prop Seg + Phase Seg 1 of the CAN protocol bit timing
specification. Bits TSEG1-3:0 specify the number of time quanta in Prop Seg + Phase Seg1.
Note: Not all combinations are valid since Prop Seg = Phase Seg1 >= Phase Seg2. The CAN
protocol states that the minimum number of Tq in a bit time shall be 8.
Note ARINC 825 states that the sample point shall not be less than 75% of the bit time. In this
case, TSeg1 should be a minimum of 5Tq for Phase Seg2 (TSeg2) = 2Tq and SJW = 1Tq.
TSEG2 bits <2:0>
0000: Not valid
0001: TSeg1 = 2Tq clock cycles
0010: TSeg1 = 3Tq clock cycles
etc.
1111: TSeg1 = 16Tq clock cycles
HI-3200 Operational Status Information
The Master Status Register may be read at any time to determine the current operational state of the HI-3200:
10
HI-31
X
MASTER STATUS REGISTER
(Address 0x800E)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
READY
R
0
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
6
5
ACTIVE
SAFE
R
R
0
0
This bit is high after RUN is asserted and the HI-3200 is in normal operating mode.
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto-
initialization fail.
4
3
RAM BUSY
PROG
R
R
0
0
This is high during the time the RAM Integrity Check is running and RAM is clearing
Indicates that the HI-3200 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
2
AUTOINIT
R
0
The HI-3200 is currently loading internal memory, registers and look-up tables from the Auto-
initialization EEPROM
1
0
-
R
R
0
0
Not used
HI-3110
The HI-3200 has detected the presence of an HI-3110 device connected to the CAN SPI
port. Note: Only valid when RUN = 1 and CANTX and/or CANRX are enabled. After HI-3110
initialization this bit is not updated in Mode 6 or 7.
HOLT INTEGRATED CIRCUITS
14
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
