HI-3200, HI-3201
CAN Bus Timing Configuration
Two registers must be programmed to define the CAN
bus data rate and bit sampling segment times. This
information is transferred directly to the HI-3110 CAN
controller’s BTR0 and BTR1 registers following the rising
edge of the RUN input.
The HI-3110 OSCIN clock frequency must be set to
achieve the desired bit rate. The HI-3200 COSC output
signal provides a convenient 24MHz clock source for the
HI-3110. For a full description of CAN Bus timing
requirements, please refer to the Holt HI-3110 data sheet.
CANBTR0
(Address 0x8030)
7 6
MSB
CANBTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP).
Bit
7:6
Name
SJW1:0
R/W
R/W
Default Description
0
These bits are used to compensate for phase shifts between different oscillators on the CAN
bus. They define the maximum number of time quanta (Tq) a bit can be shortened or
lengthened to allow the node to achieve re-synchronization to the edge of an incoming signal.
Note that the time quantum (Tq) is the single unit of time within a bit time.
The baud rate prescaler relates the HI-3110 OSCIN clock frequency, fosc, to the CAN bit time
as described in the HI-3110 data sheet.
BRP bits <5:0>
000000: BRP=1
000001: BRP=2
000010: BRP=3
000011: BRP=4
etc.
111111: BRP=64
M
TS P
E
TS
G2
EG
-2
TS
2
E
-1
TS G2
EG -0
TS
1
EG
-3
TS
1
E
-2
TS
G1
EG
-1
1-
0
5
4
3
2
1
0
LSB
5:0
BRP5:0
R/W
0
CANBTR1
(Address 0x8031)
7 6
MSB
CANBTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of
sampling points.
Bit
7
Name
SAMP
R/W
R/W
Default Description
0
This bit configures how many samples are taken per bit. 1 = three samples/bit, 0 = one
sample/bit. Bit sampling occurs at the end of Phase Seg 1.
Note: ARINC825 states that there shall be only one sample per bit
5:0
TSEG2-2:0
R/W
0
Time segment 2 length. Tseg2 = Phase Seg2 of the CAN bit timing specification. Bits
TSEG2-2:0 specify the number of time quanta in Phase Seg2.
Note: Not all combinations are valid, since Phase Seg2 must be greater than SJW.
TSEG2 bits <2:0>
000: Not valid
001: TSeg2 = 2 Tq clock cycles
010: TSeg2 = 3 Tq clock cycles
etc.
111: TSeg2 = 8 Tq clock cycles
HOLT INTEGRATED CIRCUITS
13
SA
SJ
W
SJ 1
W
BR 0
P
BR 5
P
BR 4
P
BR 3
P
BR
2
P
BR
1
P0
5
4
3
2
1
0
LSB
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
