HI-3200, HI-3201
CAN BUS TRANSMIT OPERATION
The HI-3200 is able to transmit CAN frames via an external HI-3110 CAN controller / transceiver IC. CAN frames
may be loaded for immediate transmission from the host CPU, or in a pre-programmed sequence using the integrated
CAN frame scheduler.
CAN BUS Transmit Scheduler
CAN frames to be transmitted are constructed and
launched from the CAN Bus transmit scheduler. The
scheduler is user programmed using a descriptor table to
output CAN frames in a predefined order and repetition
rate. To make best use of available memory space, three
different types (Type 1-3) of descriptor tables entry
formats are available. The user may mix descriptor types
in the table.
words to be skipped if no new data is available. CAN
frames are constructed and transmitted until an end of
sequence marker or RAM location 0x79BF is reached.
Note that if 0x79BF is reached before the frame is
completely constructed, that frame will be discarded.
Note that because the CAN bus bandwidth is shared
between all terminals on the bus, sufficient bandwidth to
transmit the entire programmed sequence of frames may
not be available in the time slot programmed. In such
circumstances the user may choose to repeat the
sequence immediately upon completion, or wait until the
next multiple of the programmed repetition rate elapses.
The CAN Indentifier ID and data byte content of each
frame transmitted is user defined and may be sourced
from the host CPU / auto-initialization EEPROM
(immediate data) or bytes from the ARINC 429 receive
memory (ARINC indexed) or CAN bus receiver memory
(CAN indexed). This allows received ARINC and / or CAN
bus data to be re-formated and re-transmited on the CAN
bus. Conditional transmission control allows sequenced
The CAN sequencer operation is controlled by the CAN
Transmit control Register:
CAN TRANSMIT CONTROL REGISTER
(Address 0x8032)
X
4
X
3
X
2
X
1
X
7
6
5
0
LSB
MSB
Bit Name
R/W Default Description
7
RUN / STOP
R/W
0
When zero, transmission from the CAN Bus transmit channel is suspended after the
currently transmitting frame is sent. When this bit is taken high, transmission starts at the
beginning of the descriptor table.
6
SKIP
R/W
0
When set to “1” instructs the transmit sequencer to wait for the next Repetition Rate Counter
rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the
cycle following completion of the prior cycle.
5
4
3
2
1
0
COSC_MASK R/W
0
0
0
0
0
0
When set to “1” this bit masks off the COSC pin.
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
Not Used
Not Used
Not Used
Not Used
Not Used
Current Sequence pointer (MSB)
Current Sequence pointer (LSB)
CAN TRANSMIT SEQUENCE POINTER
(Address 0x803E/F)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
LSB
LSB
MSB
MSB
The transmit sequence pointer is set to 0x6000 on Master
Reset. Once the RUN / STOP bit goes high, sequence
execution begins at sequence count zero (Memory
Address 0x6000). After the first word is sent, the pointer
is incremented to the address of the next descriptor in the
sequence table. This continues until the programmed
sequence is complete. The sequence pointer is then
reset to zero and program execution begins as soon the
CAN repetition rate counter time elapses.
HOLT INTEGRATED CIRCUITS
32
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
