HI-3200, HI-3201
ARINC 429 RECEIVE OPERATION
The HI-3200 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External
analog line receivers handle the physical layer connection
ARINC 429 Receive Channel Configuration
Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address
0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on. ARINC 429
Receive Control Registers may be read at any time, but can only be written when the device is in the IDLE state (RUN
input = “0”, READY output = “1”).
FFS1FFS0
ARINC 429 RX CONTROL REGISTER 0 - 7
(Address 0x8010 - 0x8017)
7
6
5
4
3
2
1
0
LSB
MSB
Bit Name
R/W Default Description
7
6
ENABLE
R/W
R/W
0
0
This bit must be set to a “1” to enableARINC 429 data reception on this channel.
HI / LO
Selects the ARINC 429 bit rate for the ARINC 429 receive channel. A “0” selects high-speed
(100Kb/s) and a “1” selects low-speed (12.5Kb/s).
5
4
PARITYEN
R/W
R/W
0
0
When this bit is a one, the 32nd receivedARINC bit is overwritten with a parity flag. The flag bit
is set to a zero when the received ARINC word, including its parity bit has an odd number of
ones. When PARITYEN is a zero, all 32-bits are received without parity checking.
DECODER
When DECODER is a “1”, bits 9 and 10 of ARINC 429 words received on this channel must
match the SD9 and SD10 bits in the register. ARINC words received that do not match the SD
conditions are ignored.
3
2
SD10
SD9
R/W
R/W
R/W
0
0
0
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 10 for the
word to be accepted.
If DECODER is set to a “1”, then this bit must match the received ARINC word bit 9 for the
word to be accepted.
1-0 FFS1:0
FFS1 and FFS0 define when this channel’s FIFO Flag is set, as shown below.
FFS1
FFS0
FLAG set condition
0
0
1
1
0
1
0
1
FLAG never set
Set FLAG if FIFO NOTEMPTYbit = “1”
Set FLAG if FIFO >Threshold value
Set FLAG is FIFO FULLbit “1”
HOLT INTEGRATED CIRCUITS
15
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
