欢迎访问ic37.com |
会员登录 免费注册
发布采购

HI-3110PSI 参数 Datasheet PDF下载

HI-3110PSI图片预览
型号: HI-3110PSI
PDF下载: 下载PDF文件 查看货源
内容描述: 航空电子与CAN收发器集成控制器 [Avionics CAN Controller with Integrated Transceiver]
分类和应用: 网络接口电信集成电路电信电路光电二极管电子控制器航空
文件页数/大小: 53 页 / 178 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
 浏览型号HI-3110PSI的Datasheet PDF文件第1页浏览型号HI-3110PSI的Datasheet PDF文件第2页浏览型号HI-3110PSI的Datasheet PDF文件第4页浏览型号HI-3110PSI的Datasheet PDF文件第5页浏览型号HI-3110PSI的Datasheet PDF文件第6页浏览型号HI-3110PSI的Datasheet PDF文件第7页浏览型号HI-3110PSI的Datasheet PDF文件第8页浏览型号HI-3110PSI的Datasheet PDF文件第9页  
HI-3110
PIN DESCRIPTIONS
SIGNAL
SCK
CS
SI
SO
INT
STAT
TXEN
FUNCTION
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
DESCRIPTION
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip Select. Data is shifted into SI and out of SO when CS is low.
SPI interface serial data input
SPI interface serial data output
Active high. Programmable interrupt output
Active high. Programmable status output.
Active high. Transmit Enable pin. When the TXEN pin is asserted, any message
in the Transmit FIFO will be automatically loaded to the Transmit buffer and sent
if the bus is available. This pin is logically ORed with the TXEN and TX1M bits
in the CTRL1 register. When the TXEN pin is reset, messages loaded to the
FIFO will not be sent until TXEN or TX1M bits are set in the CTRL1 register.
Crystal input. A parallel resonant crystal can be connected between OSCIN and
OSCOUT. If an external clock is used, it should be connected to the OSCIN pin
and the OSCOUT pin should be left floating. The internal oscillator should be
shut off by setting the OSCOFF bit in the CTRL1 register.
Crystal output. If an external clock is used, this pin should be left floating and
disabled by setting the OSCOFF bit in the CTRL1 register.
General purpose pin 1, which can be programmed to reflect the values of
interrupt and status flag bits.
General purpose pin 2, which can be programmed to reflect the values of
interrupt and status flag bits.
Clock output pin with programmable frequency divider.
VDD/2 output bias (Powered off in Sleep Mode and when the common mode
bias is greater than 25V).
CAN bus line high.
CAN bus line low.
Active High. Device Master Reset input pin. Asserting this pin resets all registers
and memory buffers to their default state at start-up.
5V supply voltage input.
3.3V supply voltage input. This supply is used to drive the host digital logic I/O.
It can either be connected directly to VDD (+5V) or a +3.3V supply.
Supply voltage ground.
INTERNAL PULL UP / DOWN
50K ohm pull-down
50K ohm pull-up
50K ohm pull-down
10
0K ohm pull-down
OSCIN
INPUT
OSCOUT
GP1
GP2
CLKOUT
SPLIT
CANH
CANL
MR
VDD
VLOGIC
GND
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
BUS I/O
BUS I/O
INPUT
POWER
POWER
POWER
50K ohm pull-down
HOLT INTEGRATED CIRCUITS
3