HI-3110
BLOCK DIAGRAM
VLOGIC
CS
SPI BUS
SCK
SI
SO
SPI DECODE/
ENCODE
REGISTERS
BIT
TIMING
VDD
GND
TRANSMIT
LOGIC & FIFO
TXEN
HISTORY
FIFO
TRANSCEIVER
GP2
GP1
STAT
INT
CANH
INTERRUPTS
AND
STATUS
ERROR
STATUS
& CONTROL
CANL
RECEIVE
LOGIC & FIFO
SPLIT
(see ordering
information)
FILTERS
OSCIN
OSCOUT
OSCILLATOR
TIME-TAG
COUNTER
MR
CLKOUT
(see ordering
information)
CLOCK DIV
OUT
HI-3110
Figure 1. HI-3110 Block Diagram
PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS
SPI PROTOCOL BLOCK
8 message FIFO with optional filters
Handles data transfers between the host and the chip Forwards message data and optional time stamp to the host
REGISTERS BLOCK
Stores configuration data
BIT TIMING BLOCK
Sets the data strobe and bit period
TRANSMIT BLOCK
Manages transmission protocol
8 message FIFO
Confirmation and time stamp of each message sent
is available in the History FIFO
RECEIVER BLOCK
Manages reception protocol
ERROR BLOCK
Detects and records errors for protocol management
STATUS AND INTERRUPT
Provides hardware and software options for managing
communications
OSCILLATOR
Configuration chooses either the crystal oscillator or and
external clock
TRANSCEIVER
Analog interface connects directly to the CAN bus
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
