欢迎访问ic37.com |
会员登录 免费注册
发布采购

HI-3001CRIF 参数 Datasheet PDF下载

HI-3001CRIF图片预览
型号: HI-3001CRIF
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, INTERFACE CIRCUIT, CDIP8, ROHS COMPLIANT, CERAMIC, DIP-8]
分类和应用: 电信电信集成电路
文件页数/大小: 13 页 / 78 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
 浏览型号HI-3001CRIF的Datasheet PDF文件第2页浏览型号HI-3001CRIF的Datasheet PDF文件第3页浏览型号HI-3001CRIF的Datasheet PDF文件第4页浏览型号HI-3001CRIF的Datasheet PDF文件第5页浏览型号HI-3001CRIF的Datasheet PDF文件第7页浏览型号HI-3001CRIF的Datasheet PDF文件第8页浏览型号HI-3001CRIF的Datasheet PDF文件第9页浏览型号HI-3001CRIF的Datasheet PDF文件第10页  
HI-3000, HI-3001, HI-3002
DC ELECTRICAL CHARACTERISTICS (cont.)
V
DD
= 5V
±
5%, Operating temperature range. Positive currents flow into the IC.
LIMITS
PARAMETER
Short-circuit steady-state output current
SYMBOL
I
OS(ss)
CONDITIONS
V
CANH
= +58V, V
CANL
open
V
CANH
= -58V, V
CANL
openV
V
CANL
= +58V, V
CANH
open
V
CANL
= -58V, V
CANH
open (See Fig. 6)
MIN
-20
-200
100
-20
TYP
MAX
20
100
200
20
UNIT
mA
mA
mA
mA
RECEIVER
Differential receiver threshold voltage
Differential hysteresis voltage
Differential hysteresis voltage in Standby mode
Input leakage current, unpowered node
Differential input resistance
Common mode input resistance
Deviation between common mode input resistance
between CANH and CANL
V
Th(Rx)(diff)
V
Hys(Rx)(diff)
V
Hys(Stb)(diff)
I
CANH
, I
CANL
R
IN(DIFF)
R
IN(CM)
R
IN(CM)(m)
− 12 V < V
CANH
, V
CANL
< + 12 V
− 12 V < V
CANH
, V
CANL
< + 12 V
− 12 V < V
CANH
, V
CANL
< + 12 V
V
DD
= V
IO
0 V
V
CANH
= V
CANL
= 5V
V
TXD
= V
DD
− 12 V < V
CANH
, V
CANL
< + 12 V
V
TXD
= V
DD
− 12 V < V
CANH
, V
CANL
< + 12 V
V
CANH
= V
CANL
500
50
500
− 200
25
15
−3
50
30
700
120
900
200
1150
+ 200
75
45
+3
mV
mV
mV
μA
%
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5V
±
5%, Operating temperature range. Positive currents flow into the IC.
LIMITS
PARAMETER
Bit time
Bit rate
Common mode input capacitance
Differential input capacitance
3
Delay TXD to bus active
Delay TXD to bus inactive
Delay bus active to RXD
Delay bus inactive to RXD
Propagation delay TXD to RXD (recessive to dominant)
Propagation delay TXD to RXD (dominant to recessive)
TXD permanent dominant time-out
TXD permanent dominant timer reset time
3
SYMBOL
t
Bit
f
Bit
C
IN(CM)
C
DIFF(CM)
t
dr(TXD)
t
df(TXD)
t
df(RXD)
t
dr(RXD)
t
Prop1
t
Prop2
t
dom
t
Rdom
CONDITIONS
MIN
1
40
TYP
MAX
25
1000
UNIT
μs
kHz
pF
pF
V
TXD
= V
DD
, 1Mbit/s data rate
V
TXD
= V
DD
, 1Mbit/s data rate
See Timing Diagrans
20
10
40
40
30
70
70
110
90
90
70
150
160
240
6
1
0.5
3
5
ns
ns
ns
ns
ns
ns
ms
μs
μs
V
TXD
= 0 V
Rising edge on TXD while in
permanent dominant state
0.3
2
Dominant time required on bus for wake up from standby
t
wake
NOTES:
1. All currents into the device pins are positive; all currents out of the device pins are negative.
2. All typicals are given for V
DD
= 5V, T
A
= 25°C.
3. Guaranteed by design but not tested.
HOLT INTEGRATED CIRCUITS
6