HI-15530
ENCODER OPERATION
The encoder requires a single clock with a frequency of
twice the desired rate applied at the SEND CLOCK input.
An auxiliary divide by six counter is provided on chip which
can be utilized to produce the SEND CLOCK by dividing
the ENCODER CLOCK.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA input with every low-to-high
transition of the ENCODER SHIFT CLOCK (3) - (4). After
the sync and the Manchester II coded data are transmitted
through the BIPOLAR ONE and BIPOLAR ZERO outputs,
the Encoder adds on an additional bit which is the parity for
that word (5). If ENCODER ENABLE is held high continu-
ously, consecutive words will be encoded without an
interframe gap. ENCODER ENABLE must go low by time
(5) as shown to prevent a consecutive word from being
encoded. At any time a low on the OUTPUT INHIBIT input
will force both bipolar outputs to a high state but will not
affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low to high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new
word.
MASTER RESET
OUTPUT
INHIBIT
SEND CLK IN
÷
6 OUT
BIPOLAR
ONE OUT
÷2
÷6
Character
Former
BIPOLAR
ZERO OUT
ENCODER CLK
Bit
Counter
SERIAL
DATA
IN
ENCODER
ENABLE
SYNC
SELECT
SEND
DATA
ENCODER
SHIFT
CLK
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
DON’T CARE
SYNC SELECT
VALID
DON’T CARE
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPLOAR
ZERO OUT
(1) (2)
15
14
13
12
11
10
3
2
1
0
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
(3)
(4) (5)
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
