HI-15530
PIN DESCRIPTIONS
SIGNAL
VALID WORD
ENCODER SHIFT CLOCK
TAKE DATA
SERIAL DATA OUT
DECODER CLOCK
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLOCK
COMMAND / DATA SYNC
FUNCTION
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
DESCRIPTION
A high output signals the receipt of a valid word
Shifts data into the encoder on a low to high transition
Output is high during receipt of data after identification of a Sync
Pulse and two valid Manchester data bits.
Received Data output in NRZ format
12x the data rate. Clock for the transition finder and synchronizer,
which generates the internal clock for the remainder of the decoder
A high input indicates the 1553 bus is in its negative state.
This pin must be held high when the Unipolar input is used
A high input indicates the 1553 bus is in the positive state.
This pin must be held low when the Unipolar input is used
Input for unipolar data to the transition finder. Must be held low when
not in use
Provides the DECODER CLOCK divided by 12, synchronized by the
recovered serial data
A high on this pin occurs during the output of decoded data which
was preceded by a Command (or Status) synchronizing character. A
low output indicates a Data synchronizing character
A high applied to this pin during a DECODER SHIFT CLOCK rising
edge resets the bit counter
0V supply
A high on this pin clears 2:1 counters in both Encoder and Decoder,
and resets the divide-by-6 circuit
Provides ENCODER CLOCK divided by 6
An active low output intended to drive the zero or negative sense of a
MIL-STD-1553 Line Driver
A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by
forcing them to inactive high states
An active low output intended to drive the one or positive sense on a
MIL-STD-1553 Line Driver
Receiver serial data at the rate of the ENCODER SHIFT CLOCK
A high on this pin initiates the encode cycle. (Subject to the
preceeding cycle being complete)
Actuates a Command Sync for an input high and a Data Sync for a
low
An active high output which enables the external source of serial
Data
Clock input at 2 times the Data rate, usualy driven by
÷
6 OUT
Input to the divide by 6 circuit. Normal frequency is Data rate x12
5V +/- 10%
DECODER RESET
GND
MASTER RESET
÷
6 OUT
BIPOLAR ZERO OUT
OUTPUT INHIBIT
BIPOLAR ONE OUT
SERIAL DATA IN
ENCODER ENABLE
SYNC SELECT
SEND DATA
SEND CLOCK IN
ENCODER CLOCK
VDD
INPUT
POWER
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
INPUT
POWER
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
