Preliminary
HT9015
Functional Description
The HT9015 is a signal chip RF IC for cordless
phone applications. It has applications for
46/49MHz cordless phones as well as CT0 cord-
less phones that have frequency bands between
20MHz and 60MHz. This chip enables external
components in the base set and hand set radio
section application circuits to be reduced.
in the shift register is sent into the latch to con-
trol the block, see the input timing for serial
data as shown below.
Serial data format of four registers
According to previous input timing Specs, the
HT9015 can be easily set up using four regis-
ters. The TX divider determines the TX PLL
locked frequency; the RX divider determines
the RX PLL locked frequency; the REF divider
determines the TX and RX PLL frequency ref-
erence which is also called channel space. The
control register is an important unit which con-
trols the radio link, voice control and power sav-
ing during base set and hand set
communication.
The HT9015 is manufactured or a special pro-
cess called BiCMOS, or bipolar process and
CMOS process. Because the RF and IF parts
need high frequency actions such as mixer,
VCO, IF amplifier and demodulator, those
parts are implemented in high performance bi-
polar circuits. The other digital functions are
designed using CMOS circuits. Sometimes this
chip is known as ²COMBO², the meaning of
COMBO is one chip combined with RF, IF and
PLL parts.
All data format contains 20 bits, but some regis-
ters need only 16 bits, They have a common
field of 20 bits data format called ²code² which
determine what data belongs to whom. See the
table below.
The HT9015 provides data latch interface con-
trolled by a microcontroller. There are four in-
ternal registers inside the HT9015; TX
(transmitter) divider, RX (receiver) Divider,
REF (reference) divider and Control Register.
All registers can be set through the data latch
control interface. The data latch control inter-
face contains DATA, CLK and STB control sig-
nals.
Code
Register
REF register
TX register
1
1
0
0
1
0
1
0
RX register
Control register
Input timing for serial data
Data is read on the timing of the rising edge of
CLK. When STB receives a high signal, DATA
Four register selection
³
0
.
m
s
2
³
m
1 s
³
0
m
. s 2
C
L
K
³
0
m
. s 2
D
A
T
A
³
0
.
m
s
1
³
0
m
. s 1
³
0
m
. s 2
S
T
B
³
0
m
. s 2
O
p
e
r
a
t
i
o
n
S
t
a
t
e
P
r
e
v
i
o
u
s
S
t
a
t
e
N
e
w
S
t
a
t
e
Figure 1 Input timing for serial data
10
April 10, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
