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HT48R01N 参数 Datasheet PDF下载

HT48R01N图片预览
型号: HT48R01N
PDF下载: 下载PDF文件 查看货源
内容描述: 小型封装8位OTP MCU [Small Package 8-Bit OTP MCU]
分类和应用:
文件页数/大小: 71 页 / 404 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R01B/02B/01N/02N  
HT48R01B/02B/01N/02N  
Mnemonic  
Rotate  
Description  
Cycles Flag Affected  
RRA [m]  
RR [m]  
Rotate Data Memory right with result in ACC  
Rotate Data Memory right  
1
1Note  
1
1Note  
1
1Note  
None  
None  
C
RRCA [m]  
RRC [m]  
RLA [m]  
RL [m]  
Rotate Data Memory right through Carry with result in ACC  
Rotate Data Memory right through Carry  
Rotate Data Memory left with result in ACC  
Rotate Data Memory left  
C
None  
None  
C
RLCA [m]  
RLC [m]  
Rotate Data Memory left through Carry with result in ACC  
Rotate Data Memory left through Carry  
1
1Note  
C
Data Move  
MOV A,[m]  
MOV [m],A  
MOV A,x  
Move Data Memory to ACC  
Move ACC to Data Memory  
Move immediate data to ACC  
1
1Note  
1
None  
None  
None  
Bit Operation  
CLR [m].i  
SET [m].i  
Clear bit of Data Memory  
Set bit of Data Memory  
1Note  
1Note  
None  
None  
Branch  
JMP addr  
SZ [m]  
Jump unconditionally  
2
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
Skip if Data Memory is zero  
1Note  
1note  
1Note  
1Note  
1Note  
1Note  
1Note  
1Note  
2
SZA [m]  
SZ [m].i  
SNZ [m].i  
SIZ [m]  
Skip if Data Memory is zero with data movement to ACC  
Skip if bit i of Data Memory is zero  
Skip if bit i of Data Memory is not zero  
Skip if increment Data Memory is zero  
Skip if decrement Data Memory is zero  
Skip if increment Data Memory is zero with result in ACC  
Skip if decrement Data Memory is zero with result in ACC  
Subroutine call  
SDZ [m]  
SIZA [m]  
SDZA [m]  
CALL addr  
RET  
Return from subroutine  
2
RET A,x  
RETI  
Return from subroutine and load immediate data to ACC  
Return from interrupt  
2
2
Table Read  
TABRDC [m]  
TABRDL [m]  
Read table (current page) to TBLH and Data Memory  
Read table (last page) to TBLH and Data Memory  
2Note  
2Note  
None  
None  
Miscellaneous  
NOP  
No operation  
1
1Note  
1Note  
1
None  
None  
CLR [m]  
Clear Data Memory  
SET [m]  
Set Data Memory  
None  
CLR WDT  
CLR WDT1  
CLR WDT2  
SWAP [m]  
SWAPA [m]  
HALT  
Clear Watchdog Timer  
TO, PDF  
TO, PDF  
TO, PDF  
None  
Pre-clear Watchdog Timer  
Pre-clear Watchdog Timer  
Swap nibbles of Data Memory  
Swap nibbles of Data Memory with result in ACC  
Enter power down mode  
1
1
1Note  
1
None  
1
TO, PDF  
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,  
if no skip takes place only one cycle is required.  
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.  
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by  
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and  
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags  
remain unchanged.  
Rev.1.10  
56  
February 12, 2010  
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