HT48R063B/064B/065B/066B
·
HT48R063B/HT48R064B/HT48R065B
¨
INTC0 Register
Bit
Name
R/W
7
6
5
4
INTF
R/W
0
3
2
1
INTE
R/W
0
0
TBF
R/W
0
T0F
R/W
0
TBE
R/W
0
T0E
R/W
0
EMI
R/W
0
¾
¾
¾
POR
Bit 7
Bit 6
unimplemented, read as ²0²
TBF: Time Base event interrupt request flag
0: inactive
1: active
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
INTF: External interrupt request flag
0: inactive
1: active
TBE: Time base event interrupt enable
0: disable
1: enable
T0E: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
INTE: external interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
·
HT48R066B
¨
INTC0 Register
Bit
Name
R/W
7
6
5
4
INTF
R/W
0
3
2
1
INTE
R/W
0
0
T1F
R/W
0
T0F
R/W
0
T1E
R/W
0
T0E
R/W
0
EMI
R/W
0
¾
¾
¾
POR
Bit 7
Bit 6
unimplemented, read as ²0²
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
INTF: External interrupt request flag
0: inactive
1: active
T1E: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
T0E: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
INTE: external interrupt enable
0: disable
1: enable
EMI: Master interrupt global enable
0: disable
1: enable
Rev. 1.00
47
April 7, 2011