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HT48R066B 参数 Datasheet PDF下载

HT48R066B图片预览
型号: HT48R066B
PDF下载: 下载PDF文件 查看货源
内容描述: 增强I / O型8位OTP MCU [Enhanced I/O Type 8-Bit OTP MCU]
分类和应用:
文件页数/大小: 84 页 / 469 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48R063B/064B/065B/066B  
System Architecture  
A key factor in the high-performance features of the  
Holtek range of microcontrollers is attributed to the inter-  
nal system architecture. The range of devices take ad-  
vantage of the usual features found within RISC  
microcontrollers providing increased speed of operation  
and enhanced performance. The pipelining scheme is  
implemented in such a way that instruction fetching and  
instruction execution are overlapped, hence instructions  
are effectively executed in one cycle, with the exception  
of branch or call instructions. An 8-bit wide ALU is used  
in practically all operations of the instruction set. It car-  
ries out arithmetic operations, logic operations, rotation,  
increment, decrement, branch decisions, etc. The inter-  
nal data path is simplified by moving data through the  
Accumulator and the ALU. Certain internal registers are  
implemented in the Data Memory and can be directly or  
indirectly addressed. The simple addressing methods of  
these registers along with additional architectural fea-  
tures ensure that a minimum of external components is  
required to provide a functional control system with  
maximum reliability and flexibility.  
Program Counter is incremented at the beginning of the  
T1 clock during which time a new instruction is fetched.  
The remaining T2~T4 clocks carry out the decoding and  
execution functions. In this way, one T1~T4 clock cycle  
forms one instruction cycle. Although the fetching and  
execution of instructions takes place in consecutive in-  
struction cycles, the pipelining structure of the  
microcontroller ensures that instructions are effectively  
executed in one instruction cycle. The exception to this  
are instructions where the contents of the Program  
Counter are changed, such as subroutine calls or  
jumps, in which case the instruction will take one more  
instruction cycle to execute.  
For instructions involving branches, such as jump or call  
instructions, two instruction cycles are required to com-  
plete instruction execution. An extra cycle is required as  
the program takes one cycle to first obtain the actual  
jump or call address and then another cycle to actually  
execute the branch. The requirement for this extra cycle  
should be taken into account by programmers in timing  
sensitive applications  
Clocking and Pipelining  
The main system clock, derived from either a Crys-  
tal/Resonator or RC oscillator is subdivided into four in-  
ternally generated non-overlapping clocks, T1~T4. The  
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Instruction Fetching  
Rev. 1.00  
15  
April 7, 2011