HT48R063B/064B/065B/066B
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
5V
4
4
+2%
+5%
MHz
MHz
Ta=25°C, R=120kW *
Ta=0~70°C, R=120kW *
-2%
-5%
5V
Ta= -40°C~85°C,
R=120kW *
fERC
System Clock (ERC)
System Clock (LXT)
5V
4
4
+7%
MHz
MHz
-7%
2.2V~ Ta= -40°C~85°C,
+11%
-11%
5.5V
R=120kW *
fLXT
32768
¾
Hz
¾
¾
¾
¾
0
¾
4000
8000
12000
15
2.2V~5.5V
3.0V~5.5V
4.5V~5.5V
kHz
kHz
kHz
kHz
kHz
Timer Input Frequency
(TCn)
fTIMER
0
¾
0
¾
3V
5V
¾
5
10
¾
¾
¾
fLIRC
tRES
LIRC Oscillator
6.5
1
13
19.5
¾
External Reset Low Pulse Width
¾
ms
tSYS
For HXT/LXT
128
¾
¾
tSST
System Start-up time Period
¾
For ERC/IRC
tSYS
2
¾
¾
(By configuration option)
tINT
Interrupt Pulse Width
1
¾
¾
¾
¾
¾
¾
¾
1
¾
2
ms
ms
ms
tLVR
Low Voltage Width to Reset
0.25
¾
RESTD Reset Delay Time
100
¾
Note: 1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
100
¾
mV
V/ms
ms
¾
¾
¾
0.035
1
¾
¾
¾
VDD raising rate to Ensure
Power-on Reset
¾
¾
¾
¾
Minimum Time for VDD Stays at
¾
V
POR to Ensure Power-on Reset
V
D
D
t
P O R
R
R
V D D
V
P
O
R
T
i
m
e
Rev. 1.00
14
April 7, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
