HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Program Memory
-
ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
512´14 bits (HT48R05A-1/HT48C05) or 1024´14 bits
(HT48R06A-1/HT48C06), addressed by the program
counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
·
Table location
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
·
Location 008H
This area is reserved for the timer/event counter inter-
rupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins ex-
ecution at location 008H.
H T 4 8 R 0 5 A -1 /H T 4 8 C 0 5
Any location in the program memory can be used as
look-up tables. The instructions
²TABRDC
[m]² (the
current page, 1 page=256 words) and
²TABRDL
[m]²
(the last page; However this statement is not valid for
the HT48R05A-1/HT48C05 devices) transfer the con-
tents of the lower-order byte to the specified data
memory, and the higher-order byte to TBLH (08H).
Only the destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the re-
maining 2 bits are read as
²0².
The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the lo-
cation must be placed in TBLP. The TBLH is read only
and cannot be restored. If the main routine and the
ISR (Interrupt Service Routine) both employ the table
read instruction, the contents of the TBLH in the main
routine are likely to be changed by the table read in-
struction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read in-
H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
In itia liz a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /C o u n te r
In te rru p t V e c to r
0 0 0 H
0 0 4 H
In itia liz a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /C o u n te r
In te rru p t V e c to r
0 0 8 H
1 F F H
2 0 0 H
3 F F H
1 4 b its
1 4 b its
N o t Im p le m e n te d
Program Memory
Instruction
TABRDC [m]
TABRDL [m]
Table Location
*9
P9
1
*8
P8
1
*7
@7
@7
*6
@6
@6
*5
@5
@5
*4
@4
@4
*3
@3
@3
*2
@2
@2
*1
@1
@1
*0
@0
@0
Table Location
Note: *9~*0: Table location bits
@7~@0: Table pointer bits
For HT48R05A-1/HT48C05, the table address location is 9 bits, i.e. from *8~*0
For HT48R06A-1/HT48C06, the table address location is 10 bits, i.e. from *9~*0
P9, P8: Current program counter bits
Rev. 1.10
6
June 9, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
