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HT48R06A-1 参数 Datasheet PDF下载

HT48R06A-1图片预览
型号: HT48R06A-1
PDF下载: 下载PDF文件 查看货源
内容描述: 高性价比的I / O型8位MCU [Cost-Effective I/O Type 8-Bit MCU]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 38 页 / 261 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Pin Assignment
P A 3
1
2
3
4
5
6
7
8
9
P A 3
1
2
3
4
5
6
7
8
P A 2
P A 1
P A 0
P B 0 /B Z
V S S
P C 0 /IN T
P C 1 /T M R
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P A 2
P A 1
P A 0
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P C 0 /IN T
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 1 /T M R
H T 4 8 R 0 5 A -1 /H T 4 8 C 0 5
H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 6 S S O P -A
H T 4 8 R 0 5 A -1 /H T 4 8 C 0 5
H T 4 8 R 0 6 A -1 /H T 4 8 C 0 6
1 8 D IP -A /S O P -A
Pad Assignment
P A 1
1 8
P A 2
1 7
P A 3
1 6
(0 ,0 )
1
2
3
4
5
V S S
P B 0 /B Z
6
7
8
R E S
P C 1 /T M R
P C 0 /IN T
9
V D D
1 0
O S C 1
1 1
P A 4
1 5
P A 5
1 4
P A 6
1 3
P A 0
P B 2
P B 1 /B Z
1 2
P A 7
O S C 2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Description
Pad Name
I/O
Options
Pull-high*
Wake-up
Description
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op-
tions).
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the
PB0 and PB1 are selected as buzzer driving outputs, the output signals come
from an internal PFD generator (shared with a timer/event counter).
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op-
tions). The external interrupt and timer input are pin-shared with the PC0 and
PC1, respectively. The external interrupt input is activated on a high to low
transition.
PA0~PA7
I/O
PB0/BZ
PB1/BZ
PB2
I/O
Pull-high*
I/O or BZ/BZ
VSS
¾
¾
PC0/INT
PC1/TMR
I/O
Pull-high*
Rev. 1.10
2
June 9, 2004