HT48R05A-1/HT48C05/HT48R06A-1/HT48C06/HT48R08A-1
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the Program Counter and SP; the others keep their orig-
inal status.
V
D
D
R
E
S
t
S
S
T
S
S
T
T
i
m
e
-
o
u
t
C
h
i
p
R
e
s
e
t
Reset Timing Chart
V
D
D
V
D D
0
.
0
1
m
F
1
0
0
k
W
1
0
0
k
R
E
S
R
E
S
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
m
0 . 1 F
1
0
k
B
a
s
i
c
H
i
-
n
o
i
s
e
R
e
s
e
t
R
e
s
e
t
m
0 . 1 F
C
i
r
c
u
i
t
C
i
r
c
u
i
t
Reset Circuit
Note: Most applications can use the Basic Reset Cir-
cuit as shown, however for applications with ex-
tensive noise, it is recommended to use the
Hi-noise Reset Circuit.
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
R
E
S
C
o
l
d
R
e
s
e
t
S
S
T
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
1
C
o
u
n
t
e
r
S
y
s
t
e
m
R
e
s
e
t
Reset Configuration
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
TO PDF
RESET Conditions
RES reset during power-up
0
u
0
1
1
0
u
1
u
1
Reset
RES reset during normal operation
RES wake-up HALT
There are three ways in which a reset can occur:
·
·
·
RES reset during normal operation
RES reset during HALT
WDT time-out during normal operation
WDT wake-up HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.51
11
December 30, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
