HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
● ANCSR1 Register
Bit
Name
R/W
7
PCR15
R/W
0
6
PCR14
R/W
0
5
PCR13
R/W
0
4
PCR1ꢃ
R/W
0
3
PCR11
R/W
0
2
PCR10
R/W
0
1
PCR9
R/W
0
0
PCR8
R/W
0
POR
Bit 7
PCR15: Define PE7 is A/D input or not
0: Not A/D input
1: A/D input, AN15
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCR14: Define PE6 is A/D input or not
0: Not A/D input
1: A/D input, AN14
PCR13: Define PE5 is A/D input or not
0: Not A/D input
1: A/D input, AN13
PCR12: Define PE4 is A/D input or not
0: Not A/D input
1: A/D input, AN12
PCR11: Define PE3 is A/D input or not
0: Not A/D input
1: A/D input, AN11
PCR10: Define PE2 is A/D input or not
0: Not A/D input
1: A/D input, AN10
PCR9: Define PE1 is A/D input or not
0: Not A/D input
1: A/D input, AN9
PCR8: Define PE0 is A/D input or not
0: Not A/D input
1: A/D input, AN8
The START bit in the register is used to start and reset the A/D converter. When the sets this bit
from low to high and then low again, an analog to digital conversion cycle will be initiated. When
the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register
will be set to a "1" and the analog to digital converter will be reset. It is the START bit that is used
to control the overall start operation of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to "0" by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, is first divided
by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in
the ACSR register.
Rev. 1.00
ꢄꢄ
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
