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HT46R0662G 参数 Datasheet PDF下载

HT46R0662G图片预览
型号: HT46R0662G
PDF下载: 下载PDF文件 查看货源
内容描述: 增强A / D型8位OTP MCU与OPA [Enhanced A/D Type 8-Bit OTP MCU with OPA]
分类和应用:
文件页数/大小: 136 页 / 748 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R064G/065G/0662G  
Enhanced A/D Type 8-Bit OTP MCU with OPA  
Operational Amplifiers  
There are two fully integrated Operational Amplifiers in these devices, OPA0 and OPA1. These OPAs  
can be used for user specified analog signal processing. The OPAs can be disabled or enabled entirely  
under software control using internal registers. With specific control registers, some OPA related  
applications can be easily implemented, such as Unity Gain Buffer, Non-Inverting Amplifier,  
Inverting Amplifier and various kinds of filters, etc.  
Comparator & Operational Amplifier Registers  
The internal Operational Amplifiers are fully under the control of internal registers, COPA0C,  
COPA1C, COPA2C, COPA3C, OPA0OC and OPA1OC. These registers control the enable/disable  
function, input path selection, gain control, polarity and calibration function.  
Operational Amplifier Operation  
The advantages of multiple switches and input path options, various reference voltage selection, up to 8  
kinds of internal software gain control, output with interrupt function, offset reference voltage calibration  
function and power down control for low power consumption enhance the flexibility of these two OPAs  
to suit a wide range of application possibilities.  
Note that the EA0I, EA1I interrupt control bits should be set to ²0² before entering halt mode for  
power saving.  
The following block diagram illustrates the main functional blocks of the OPAs and Comparator in this  
device.  
S12  
EA0I  
S11  
A0N  
A0X  
To OPA0 interrupt  
A0  
A0P  
0.7VDD  
0.5VDD  
0.1VDD  
MA0P  
MUX  
A0PS[2:0]  
A1NS[1:0]  
S13  
A0X  
S21  
R1  
10K  
S22  
S23  
R2  
500K  
MA1N  
A1N  
A1P  
MUX  
EA1I  
A1X  
To OPA1 interrupt  
A1  
0.7VDD  
0.5VDD  
0.1VDD  
MA1P  
MUX  
CINTS[1:0]  
=00: rasing edge  
=01: falling edge  
=10: both edge  
A1PS[2:0]  
CNS[1:0]  
Edge  
control  
S24  
to interrupt  
A1X  
TC0 pin  
MCN  
MUX  
POL  
CN  
CP  
mux  
To timer 0 external  
clock input  
debounce  
C
CX  
(COUT)  
TMR0S  
0.7VDD  
0.5VDD  
0.1VDD  
MCP  
MUX  
CPS[2:0]  
CX  
Rev. 1.00  
77  
March 3, 2011