HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by
the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the
Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer will
result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two
internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both a
configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory.
Configuration
Option
CTRL1
WDT
Register
Function
Disable
Disable
Enable
Disable
Enable
x
OFF
ON
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition
when the device is powered up. Although any other data written to WDTEN3~WDTEN0 will ensure
that the Watchdog Timer is enabled, for maximum protection it is recommended that the value
0101B is written to these bits.
The Watchdog Timer clock can emanate from three different sources, selected by configuration option.
These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Sleep Mode the
instruction clock is stopped, therefore if the configuration options have selected fSYS/4 as the Watchdog
Timer clock source, the Watchdog Timer will cease to function. For systems that operate in noisy
environments, using the LIRC or the LXTas the clock source is therefore the recommended choice. The
division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1
and WS2. If the Watchdog Timer internal clock source is selected and with the WS0, WS1 and WS2 bits
of the WDTS register all set high, the prescaler division ratio will be 1:128, which will give a maximum
time-out period.
Watchdog Timer
Rev. 1.00
33
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
