HT46R064B/065B/066B
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System Clock Configurations
·
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or LXT oscillator. The WDT will stop if its clock source
originates from the system clock.
For all devices, when the system enters the Sleep or Idle
Mode, the high frequency system clock will always stop
running. The accompanying tables shows the relation-
ship between the CLKMOD bit, the HALT instruction and
the high/low frequency oscillators. The CLMOD bit can
change normal or Slow Mode.
·
·
The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
·
Operating Mode Control
OSC1/OSC2 Configuration
Standby Current Considerations
Operating
Mode
HIRC + LXT
HIRC LXT
As the main reason for entering the Idle/Sleep Mode is
to keep the current consumption of the MCU to as low a
value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised.
HXT ERC HIRC
Normal
Slow
Run
Run
Run
Run
Run
Stop Run
¾
¾
¾
Sleep
Stop Stop Stop Stop Run
²¾² unimplemented
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or con-
nected only to external circuits that do not draw current,
such as other CMOS inputs.
Mode Switching
The devices are switched between one mode and an-
other using a combination of the CLKMOD bit in the
CTRL0 register and the HALT instruction. The CLKMOD
bit chooses whether the system runs in either the Nor-
mal or Slow Mode by selecting the system clock to be
sourced from either a high or low frequency oscillator.
The HALT instruction forces the system into either the
Idle or Sleep Mode, depending upon whether the LXT
oscillator is running or not. The HALT instruction oper-
ates independently of the CLKMOD bit condition.
If the configuration options have enabled the Watchdog
Timer internal oscillator LIRC then this will continue to
run when in the Idle/Sleep Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. The LXT, if configured for use, will
also consume a limited amount of power, as it continues
to run when the device enters the Idle/Sleep Mode. To
keep the LXT power consumption to a minimum level
the LXTLP bit in the CTRL0 register, which controls the
low power function, should be set high.
When a HALT instruction is executed and the LXT oscil-
lator is not running, the system enters the Sleep mode
the following conditions exist:
·
The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
·
The Data Memory contents and registers will maintain
their present condition.
Rev. 1.00
29
April 8, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
