HT46R46/C46/R47/C47/R48/R49
Pulse Width Modulator
Each microcontroller in the Cost-effective A/D Type
MCU series contains either one or two Pulse Width
Modulation, PWM, outputs. Useful for such applications
such as motor speed control, the PWM function pro-
vides outputs with a fixed frequency but with a duty cycle
that can be varied by setting particular values into the
corresponding PWM register.
the PWM cycle frequency and the PWM modulation fre-
quency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256, while the
PWM modulation frequency for the 6+2 mode of opera-
tion will be fSYS/64.
PWM
PWM Cycle
Frequency
PWM Cycle
Duty
Modulation
Frequency
PWM Output Register
Device
Channels
Mode
Pins
Name
(PWM register
value)/256
PD0/
PD1
PWM0/
PWM1
f
SYS/64
fSYS/256
HT46R49
2
1
6+2
Other
6+2
PD0
PWM
Devices
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM,
PWM0 or PWM1 register, has 256 clock periods. How-
ever, in the 6+2 PWM Mode, each PWM cycle is subdi-
vided into four individual sub-cycles known as
modulation cycle 0~modulation cycle 3, denoted as ²i²
in the table. Each one of these four sub-cycles contains
64 clock cycles. In this mode, a modulation frequency
increase by a factor of four is achieved. The 8-bit PWM,
PWM0 or PWM1 register value, which represents the
overall duty cycle of the PWM waveform, is divided into
two groups. The first group which consists of bit2~bit7 is
denoted here as the DC value. The second group which
consists of bit0~bit1 is known as the AC value. In the
6+2 PWM mode, the duty cycle value of each of the four
modulation sub-cycles is shown in the following table.
For devices with one PWM output, a single register, lo-
cated in the Data Memory is assigned to the Pulse Width
Modulator and is known as the PWM register. For de-
vices with two PWM outputs, two registers are provided
and are known as PWM0 and PWM1. It is in these regis-
ters, that the 8-bit value, which represents the overall
duty cycle of one modulation cycle of the output wave-
form, should be placed. To increase the PWM modula-
tion frequency, each modulation cycle is modulated into
four individual modulation sub-sections, known as the
6+2 mode. Note that it is only necessary to write the re-
quired modulation value into the corresponding PWM
register as the subdivision of the waveform into its
sub-modulation cycles is implemented automatically
within the microcontroller hardware. For all devices, the
DC
PWM clock source is the system clock fSYS
.
Parameter
AC (0~3)
i<AC
(Duty Cycle)
This method of dividing the original modulation cycle
into a further 4 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
DC+ 1
64
Modulation cycle i
(i=0~3)
DC
64
i³AC
6+2 Mode Modulation Cycle Values
Rev. 1.00
25
April 18, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
