HT46R23/HT46C23
0 0 0 H
0 0 4 H
0 0 8 H
0 0 C H
0 1 0 H
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
A /D
C o n v e r te r In te r r u p t S u b r o u tin e
I
2
C
B U S In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
address is match or completed one byte of data trans-
fer, and if the interrupt is enable and the stack is not
full, the program begins execution at location 010H.
·
Table location
n 0 0 H
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F 0 0 H
F F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at lo-
cation 000H.
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
·
Location 008H
Any location in the PROM space can be used as
look-up tables. The instructions
²TABRDC
[m]² (the
current page, 1 page=256 words) and
²TABRDL
[m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as
²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before ac-
cessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Rou-
tine) both employ the table read instruction, the con-
tents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simulta-
neously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the opera-
tion. These areas may function as normal program
memory depending upon the requirements.
Stack Register
-
STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
This area is reserved for the timer/event counter inter-
rupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 008H.
·
Location 00CH
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
·
Location 010H
This area is reserved for the I
2
C Bus interrupt service
program. If the I
2
C Bus interrupt resulting from a slave
Table Location
Instruction
*11
TABRDC [m]
TABRDL [m]
P11
1
*10
P10
1
*9
P9
1
*8
P8
1
*7
@7
@7
*6
@6
@6
*5
@5
@5
*4
@4
@4
*3
@3
@3
*2
@2
@2
*1
@1
@1
*0
@0
@0
Table Location
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
7
P11~P8: Current program counter bits
Rev. 1.90
July 13, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
