欢迎访问ic37.com |
会员登录 免费注册
发布采购

HT46R23(28SKDIP) 参数 Datasheet PDF下载

HT46R23(28SKDIP)图片预览
型号: HT46R23(28SKDIP)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDIP28]
分类和应用: 可编程只读存储器微控制器光电二极管
文件页数/大小: 48 页 / 339 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
 浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第7页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第8页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第9页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第10页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第12页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第13页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第14页浏览型号HT46R23(28SKDIP)的Datasheet PDF文件第15页  
HT46R23/HT46C23  
Oscillator Configuration  
(system clock divided by 4) decided by options. This  
timer is designed to prevent a software malfunction or  
sequence jumping to an unknown location with unpre-  
dictable results. The watchdog timer can be disabled by  
an option. If the watchdog timer is disabled, all the exe-  
cutions related to the WDT result in no operation.  
There are two oscillator circuits in the microcontroller.  
V
D
D
4
7
0
p
F
O
S
C
1
O
S
C
1
Once an internal WDT oscillator (RC oscillator with pe-  
riod 65ms/@5V normally) is selected, it is divided by  
212~215 (by options to get the WDT time-out period).  
The minimum period of WDT time-out period is about  
300ms~600ms. This time-out period may vary with tem-  
perature, VDD and process variations. By selection the  
WDT options, longer time-out periods can be realized. If  
the WDT time-out is selected 215, the maximum time-out  
period is divided by 215~216 about 2.1s~4.3s.  
f
S
Y
S
/
4
O
S
C
2
O
S
C
2
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
R
C
O
s
c
i
l
l
a
t
o
r
System Oscillator  
Both are designed for system clocks, namely the RC os-  
cillator and the Crystal oscillator, which are determined  
by options. No matter what oscillator type is selected,  
the signal provides the system clock. The HALT mode  
stops the system oscillator and ignores an external sig-  
nal to conserve power.  
If the WDT oscillator is disabled, the WDT clock may still  
come from the instruction clock and operate in the same  
manner except that in the halt state the WDT may stop  
counting and lose its protecting purpose. In this situation  
the logic can only be restarted by external logic. If the  
device operates in a noisy environment, using the  
on-chip RC oscillator (WDT OSC) is strongly recom-  
mended, since the HALT will stop the system clock.  
If an RC oscillator is used, an external resistor between  
OSC1 and VSS is required and the resistance must  
range from 30kW to 750kW. The system clock, divided by  
4, is available on OSC2 with pull-high resistor, which can  
be used to synchronize external logic. The RC oscillator  
provides the most cost effective solution. However, the  
frequency of oscillation may vary with VDD, tempera-  
tures and the chip itself due to process variations. It is,  
therefore, not suitable for timing sensitive operations  
where an accurate oscillator frequency is desired.  
The WDT overflow under normal operation will initialize  
²chip reset² and set the status bit TO. Whereas in the halt  
mode, the overflow will initialize a ²warm reset² only the  
program counter and SP are reset to zero. To clear the  
contents of WDT, three methods are adopted; external re-  
set (a low level to RES), software instructions, or a HALT  
instruction. The software instructions include CLR WDT  
and the other set - CLR WDT1 and CLR WDT2. Of these  
two types of instruction, only one can be active depending  
on the options - ²CLR WDT times selection option². If the  
²CLR WDT² is selected (i.e. CLRWDT times equal one),  
any execution of the CLR WDT instruction will clear the  
WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen  
(i.e. CLRWDT times equal two), these two instructions  
must be executed to clear the WDT; otherwise, the WDT  
may reset the chip because of time-out.  
If the Crystal oscillator is used, a crystal across OSC1  
and OSC2 is needed to provide the feedback and phase  
shift required for the oscillator, and no other external  
components are required. Instead of a crystal, a resona-  
tor can also be connected between OSC1 and OSC2 to  
get a frequency reference, but two external capacitors in  
OSC1 and OSC2 are required (If the oscillating fre-  
quency is less than 1MHz).  
The WDT oscillator is a free running on-chip RC oscilla-  
tor, and no external components are required. Even if  
the system enters the power down mode, the system  
clock is stopped, but the WDT oscillator still works with a  
period of approximately 65ms@5V. The WDT oscillator  
can be disabled by options to conserve power.  
If the WDT time-out period is selected fs/212 (by options),  
the WDT time-out period ranges from fs/212~fs/213, since  
the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² in-  
structions only clear the last two stages of the WDT.  
Watchdog Timer - WDT  
The clock source of the WDT is implemented by an dedi-  
cated RC oscillator (WDT oscillator) or instruction clock  
S
y
s
t
e
m
C
l
o
c
k
/
4
8
s
f / 2  
M
a
s
k
f
s
W
D
T
P
r
e
s
c
a
l
e
r
D
i
v
i
d
e
r
o
p
t
i
o
n
s
e
l
e
c
t
W
D
T
C
K
T
C
K
T
T
f
f
f
f
i
m
e
-
o
u
t
R
e
s
e
t
M
a
s
k
O
p
t
i
o
n
O
S
C
1
1
1
1
5
4
3
2
1
1
1
1
6
5
4
3
R
R
s
s
s
s
/
/
/
/
2
2
2
2
~
~
~
~
f
f
f
f
s
s
s
s
/
/
/
/
2
2
2
2
W
D
T
C
l
e
a
r
Watchdog Timer  
Rev. 1.90  
11  
July 13, 2005