HT46R23/HT46C23
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay. The functional unit chip reset status
are shown below.
Program Counter
Interrupt
000H
Disable
Clear. After master reset, WDT
begins counting
WDT
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
Timer/Event Counter Off
Input/Output Ports
Stack Pointer
Input mode
Points to the top of the stack
The registers states are summarized in the following table.
Reset
WDT Time-out
RES Reset
RES Reset
WDT Time-out
(HALT)*
Register
(Power On)
(Normal Operation) (Normal Operation)
(HALT)
xxxx xxxx
xxxx xxxx
00-0 1000
TMRL
TMRH
TMRC
xxxx xxxx
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1000
xxxx xxxx
xxxx xxxx
00-0 1000
uuuu uuuu
uuuu uuuu
uu-u uuuu
Program
Counter
000H
000H
000H
000H
000H
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
-000 0000
---0 ---0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--1u uuuu
-000 0000
---0 ---0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
-000 0000
---0 ---0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
---0 ---0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
---u ---u
MP1
ACC
TBLP
TBLH
STATUS
INTC0
INTC1
PA
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
---1 1111
---- --11
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
---1 1111
---- --11
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
---1 1111
---- --11
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
---1 1111
---- --11
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
---u uuuu
---- --uu
PAC
PB
PBC
PC
PCC
PD
PDC
---- --11
---- --11
---- --11
---- --11
---- --uu
PWM0
PWM1
HADR
HCR
HSR
xxxx xxxx
xxxx xxxx
xxxx xxx-
0--0 0---
xxxx xxxx
xxxx xxxx
xxxx xxx-
0--0 0---
xxxx xxxx
xxxx xxxx
xxxx xxx-
0--0 0---
xxxx xxxx
xxxx xxxx
xxxx xxx-
0--0 0---
uuuu uuuu
uuuu uuuu
uuuu uuu-
u--u u---
100- -0-1
xxxx xxxx
xx-- ----
100- -0-1
xxxx xxxx
xx-- ----
100- -0-1
xxxx xxxx
xx-- ----
100- -0-1
xxxx xxxx
xx-- ----
uuu- -u-u
uuuu uuuu
uuuu ----
HDR
ADRL
ADRH
ADCR
ACSR
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
uuuu uuuu
uuuu uuuu
u--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 2.11
13
December 29, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
