HT46R14
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.2V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
0
4000
8000
4000
8000
180
kHz
kHz
kHz
kHz
ms
¾
¾
¾
¾
90
65
¾
fSYS
System Clock
3.3V~5.5V
¾
2.2V~5.5V
¾
Timer I/P Frequency
(TMR0/TMR1)
fTIMER
3.3V~5.5V
0
¾
3V
5V
¾
45
32
1
¾
¾
¾
tWDTOSC
Watchdog Oscillator Period
130
ms
tRES
tSST
External Reset Low Pulse Width
System Start-up Timer Period
¾
ms
Power-up or Wake-up
from HALT
*tSYS
1024
¾
¾
¾
tINT
Interrupt Pulse Width
A/D Clock Period
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
76
32
¾
¾
¾
¾
¾
3
ms
ms
tAD
1
tADC
tADCS
tCOMP
tAD
tAD
A/D Conversion Time
A/D Sampling Time
¾
¾
¾
Comparator Response Time
ms
Note: *tSYS=1/fSYS
Functional Description
Execution Flow
Program Counter - PC
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are exe-
cuted and its contents specify full range of program
memory.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are in-
cremented by one. The program counter then points to the
memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Rev. 1.10
5
November 24, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
