HT46R064B/065B/066B
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Idle/Sleep Mode,
when a Watchdog Timer time-out occurs, the device will
be woken up, the TO bit in the status register will be set
and only the Program Counter and Stack Pointer will be
reset. Three methods can be adopted to clear the con-
tents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT in-
struction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second op-
tion, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will
have no effect, only the execution of a ²CLR WDT2² in-
struction will clear the Watchdog Timer. Similarly after
the ²CLR WDT2² instruction has been executed, only a
successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
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Watchdog Timer
·
WDTS Register
Bit
Name
R/W
7
6
5
4
3
2
1
0
WS2
R/W
1
WS1
R/W
1
WS0
R/W
1
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POR
Bit 7~3 :
Bit 2~0
unimplemented, read as ²0²
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
Rev. 1.10
33
October 23, 2012
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
