HT46R01/HT46R02/HT46R03
Setting up the various Watchdog Timer options are con-
trolled via the configuration options and two internal reg-
isters WDTS and CTRL1. Enabling the Watchdog Timer
can be controlled by both a configuration option and the
WDTEN bits in the CTRL1 internal register in the Data
Memory.
recommended choice. No matter which clock source is
selected, it is further divided by 256 via an internal 8-bit
counter and then by a 7-bit prescaler to give longer
time-out periods. The division ratio of the prescaler is
determined by bits 0, 1 and 2 of the WDTS register,
known as WS0, WS1 and WS2. If the Watchdog Timer
internal clock source is selected and with the WS0, WS1
and WS2 bits of the WDTS register all set high, the
prescaler division ratio will be 1:128, which will give a
maximum time-out period of about 2.1s.
Configuration
Option
CTRL1
WDT
Register
Function
Disable
Enable
Disable
Enable
Disable
Disable
Enable
Enable
OFF
ON
ON
ON
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Power Down Mode,
when a Watchdog Timer time-out occurs, the device will
be woken up, the TO bit in the status register will be set
and only the Program Counter and Stack Pointer will be
reset. Three methods can be adopted to clear the con-
tents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT in-
struction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second op-
tion, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have
no effect, only the execution of a ²CLR WDT2² instruc-
tion will clear the Watchdog Timer. Similarly after the
²CLR WDT2² instruction has been executed, only a suc-
cessive ²CLR WDT1² instruction can clear the Watch-
dog Timer.
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits
WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B. This will be the condition
when the device is powered up. Although any other data
written to WDTEN3~WDTEN0 will ensure that the
Watchdog Timer is enabled, for maximum protection it is
recommended that the value 0101B is written to these
bits.
The Watchdog Timer clock can emanate from three dif-
ferent sources, selected by configuration option. These
are its own fully integrated dedicated internal oscillator,
the RTC or fSYS/4. The Watchdog Timer dedicated inter-
nal clock source is an internal oscillator which has an
approximate period of 65ms at a supply voltage of 5V.
However, it should be noted that this specified internal
clock period can vary with VDD, temperature and pro-
cess variations. The other Watchdog Timer clock source
options are the fSYS/4 clock and the RTC. It is important
to note that when the system enters the Power Down
Mode the instruction clock is stopped, therefore if the
configuration options have selected fSYS/4 as the
Watchdog Timer clock source, the Watchdog Timer will
cease to function. For systems that operate in noisy en-
vironments, using the internal Watchdog Timer internal
oscillator or the RTC as the clock source is therefore the
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Rev. 1.00
44
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
