HT46R01/HT46R02/HT46R03
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. The RTC, if configured for use, will
also consume a limited amount of power, as it continues
to run when the device enters the Power Down Mode. To
keep the RTC power consumption to a minimum level
the QOSC bit in the CTRL0 register, which controls the
quick start up function, should be set high. If any I/O pins
are configured as A/D analog inputs using the channel
configuration bits in the ADCR register, then the A/D
converter will be turned on and a certain amount of
power will be consumed. It may be therefore desirable
before entering the Power Down Mode to ensure that
the A/D converter is powered down by ensuring that any
A/D input pins are setup as normal logic inputs with
pull-high resistors.
Pins PA0 to PA6 can be setup via an individual configu-
ration option to permit a negative transition on the pin to
wake-up the system. When a PA0 to PA6 pin wake-up
occurs, the program will resume execution at the in-
struction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² be-
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
Wake-up
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
·
·
·
·
An external reset
An external falling edge on PA0 to PA6
A system interrupt
A WDT overflow
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Watchdog Timer
The Watchdog Timer, also known as the WDT, is pro-
vided to inhibit program malfunctions caused by the pro-
gram jumping to unknown locations due to certain
uncontrollable external events such as electrical noise.
It operates by providing a device reset when the Watch-
dog Timer counter overflows. Note that if the Watchdog
Timer function is not enabled, then any instructions re-
lated to the Watchdog Timer will result in no operation.
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Watchdog Timer
Rev. 1.00
43
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
