HT46F46E/HT46F47E/HT46F48E/HT46F49E
where the related interrupt is enabled and the stack is
ture, VDD and process variations. As the clear instruc-
tion only resets the last stage of the divider chain, for this
reason the actual division ratio and corresponding
Watchdog Timer time-out can vary by a factor of two.
The exact division ratio depends upon the residual value
in the Watchdog Timer counter before the clear instruc-
tion is executed. It is important to realise that as there
are no independent internal registers or configuration
options associated with the length of the Watchdog
Timer time-out, it is completely dependent upon the fre-
quency of fSYS/4 or the internal WDT oscillator.
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² be-
fore entering the Power Down Mode, the wake-up func-
tion of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
If the fSYS/4 clock is used as the WDT clock source, it
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
Watchdog Timer
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a ²HALT² instruction.
The Watchdog Timer is provided to prevent program mal-
functions or sequences from jumping to unknown loca-
tions, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is sup-
plied by one of two sources selected by configuration op-
tion: its own self contained dedicated internal WDT
oscillator or fSYS/4. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to its
operation will result in no operation.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle ²CLR WDT² instruction while the second is to use the
two commands ²CLR WDT1² and ²CLR WDT2². For the
first option, a simple execution of ²CLR WDT² will clear
the WDT while for the second option, both ²CLR WDT1²
and ²CLR WDT2² must both be executed to successfully
clear the WDT. Note that for this second option, if ²CLR
WDT1² is used to clear the WDT, successive executions
of this instruction will have no effect, only the execution of
a ²CLR WDT2² instruction will clear the WDT. Similarly
after the ²CLR WDT2² instruction has been executed,
only a successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
In the Cost-Effective A/D Flash Type with EEPROM se-
ries of microcontrollers, all Watchdog Timer options,
such as enable/disable, WDT clock source and clear in-
struction type all selected through configuration options.
There are no internal registers associated with the WDT
in the Cost-Effective A/D Flash Type MCU series. One
of the WDT clock sources is an internal oscillator which
has an approximate period of 65ms at a supply voltage
of 5V. However, it should be noted that this specified in-
ternal clock period can vary with VDD, temperature and
process variations. The other WDT clock source option
is the fSYS/4 clock. Whether the WDT clock source is its
own internal WDT oscillator, or from fSYS/4, it is divided
by 213~216 (by options to get the WDT time-out period).
The max time out period is around 4.3s when the 216 is
selected. This time-out period may vary with tempera-
C
C
L
L
R
R
W
W
D
D
T
T
1
2
F
F
l
l
a
a
g
g
C
l
e
a
r
W
D
T
T
y
p
e
C
o
n
f
i
g
u
r
a
t
i
o
n
O
p
t
i
o
n
1
o
r
2
I
n
s
t
r
u
c
t
i
o
n
s
C
L
R
f
S
Y
/
S
4
W
D
T
C
L
o
c
k
S
o
u
r
c
e
1
6
-
b
i
t
C
o
u
n
t
e
r
C
o
n
f
i
g
r
u
r
a
t
i
o
n
O
p
t
i
o
n
W
D
T
O
s
c
i
l
l
a
t
o
C
o
n
f
i
g
O
W
p
D
t
T
i
o
T
n
i
m
e
-
o
u
t
1
3
1
4
1
5
1
6
S
r / ) f 2
(
2
/
S
,
f
/
2
S
,
f
/
2
S
f
o
Watchdog Timer
Rev. 1.40
55
July 28, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
