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HT45R04E 参数 Datasheet PDF下载

HT45R04E图片预览
型号: HT45R04E
PDF下载: 下载PDF文件 查看货源
内容描述: [适用于安防系列(烟感器、温感器、家用一 氧化碳测试器)等产品的 IC:HT45R04E。 工作电压:2.2V~5.5V ;工作频率:400Kz---2MHz(当fsys=455kHz时,VDD=+5V时 IDD<200uA) 1. 最多可有13 个双向输入/输出口 , 18-pin SOP 封装 2. 1 个与输入/输出口共用引脚的外部中断输入 3. 8 位可编程定时/计数器,具有溢出中断和7 级预分频器 4. 内置晶体和RC 振荡电路 5. 看门狗定时器 6. 1024×14Bits 程序存储器ROM 7. 64×8Bits 数据存储器RAM 8. 128×8Bits 数据存储器EEPROM,符合IIC通信协议(使用方法同24C01一致) 9. 具有PFD 功能,可以用来发声 10. HALT 和唤醒功能可降低功耗 11. 4 层硬件堆栈 12. 4 通道8 位解析度的A/D 转换器 13. 查表指令,表格内容字长14 位 14. 63 条指令,包含位操作指令 15. 指令执行时间为1 或2 个指令周期]
分类和应用: 晶体转换器预分频器计数器存储测试通信可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 43 页 / 2641 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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Preliminary  
HT45R04/HT45R04E  
Instruction  
Cycle  
Flag  
Affected  
Mnemonic  
Branch  
Description  
JMP addr  
SZ [m]  
Jump unconditionally  
2
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
Skip if data memory is zero  
1(2)  
1(2)  
1(2)  
1(2)  
1(3)  
1(3)  
1(2)  
1(2)  
2
SZA [m]  
SZ [m].i  
SNZ [m].i  
SIZ [m]  
Skip if data memory is zero with data movement to ACC  
Skip if bit i of data memory is zero  
Skip if bit i of data memory is not zero  
Skip if increment data memory is zero  
Skip if decrement data memory is zero  
Skip if increment data memory is zero with result in ACC  
Skip if decrement data memory is zero with result in ACC  
Subroutine call  
SDZ [m]  
SIZA [m]  
SDZA [m]  
CALL addr  
RET  
Return from subroutine  
2
RET A,x  
RETI  
Return from subroutine and load immediate data to ACC  
Return from interrupt  
2
2
Table Read  
Read ROM code (current page) to data memory and TBLH  
Read ROM code (last page) to data memory and TBLH  
(This instruction is not valid for HT48R05A-1/HT48C05)  
TABRDC [m]  
TABRDL [m]  
2(1)  
2(1)  
None  
None  
Miscellaneous  
NOP  
No operation  
1
1(1)  
1(1)  
1
None  
None  
CLR [m]  
Clear data memory  
SET [m]  
Set data memory  
None  
CLR WDT  
CLR WDT1  
CLR WDT2  
SWAP [m]  
SWAPA [m]  
HALT  
Clear Watchdog Timer  
TO,PDF  
TO(4),PDF(4)  
TO(4),PDF(4)  
None  
Pre-clear Watchdog Timer  
Pre-clear Watchdog Timer  
Swap nibbles of data memory  
Swap nibbles of data memory with result in ACC  
Enter power down mode  
1
1
1(1)  
1
None  
1
TO,PDF  
Note: x: Immediate data  
m: Data memory address  
A: Accumulator  
i: 0~7 number of bits  
addr: Program memory address  
Ö: Flag is affected  
-: Flag is not affected  
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle  
(four system clocks).  
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more  
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.  
(1) and (2)  
(3)  
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the  
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.  
Otherwise the TO and PDF flags remain unchanged.  
Rev. 0.00  
26  
December 30, 2004  
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