HT45F12
8-Bit Flash MCU with Op Amps & Comparators
SLOW Mode to NORMAL Mode Switching
InꢀSLOWꢀModeꢀtheꢀsystemꢀusesꢀtheꢀLIRCꢀlowꢀspeedꢀsystemꢀoscillator.ꢀToꢀswitchꢀbackꢀtoꢀtheꢀ
NORMALꢀMode,ꢀwhereꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀused,ꢀtheꢀHLCLKꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ
“1”ꢀorꢀHLCLKꢀbitꢀisꢀ“0”,ꢀbutꢀLCKS2~LCKS0ꢀisꢀsetꢀtoꢀ“010”,ꢀ“011”,ꢀ“100”,ꢀ“101”,ꢀ“110”ꢀorꢀ“111”.ꢀ
Asꢀaꢀcertainꢀamountꢀofꢀtimeꢀwillꢀbeꢀrequiredꢀforꢀtheꢀhighꢀfrequencyꢀclockꢀtoꢀstabilise,ꢀtheꢀstatusꢀofꢀ
theꢀHTOꢀbitꢀisꢀchecked.ꢀTheꢀamountꢀofꢀtimeꢀrequiredꢀforꢀhighꢀspeedꢀsystemꢀoscillatorꢀstabilizationꢀ
dependsꢀuponꢀwhichꢀhighꢀspeedꢀsystemꢀoscillatorꢀtypeꢀisꢀused.
Entering the SLEEP0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀSLEEP0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSYSMODꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀ
WDTꢀisꢀoff.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀ
willꢀoccur:
Theꢀsystemꢀclock,ꢀWDTꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀ
willꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstoppedꢀ
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the SLEEP1 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀSLEEP1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSYSMODꢀregisterꢀequalꢀtoꢀ“0”ꢀandꢀtheꢀWDTꢀ
isꢀon.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur
:
•ꢀ TheꢀsystemꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ
“HALT”ꢀinstruction,ꢀbutꢀtheꢀWDTꢀwillꢀremainꢀwithꢀtheꢀclockꢀsourceꢀcomingꢀfromꢀtheꢀfLꢀclock.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀasꢀtheꢀWDTꢀisꢀenabled.
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
Entering the IDLE0 Mode
ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ“HALT”ꢀ
instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSYSMODꢀregisterꢀequalꢀtoꢀ“1”ꢀandꢀtheꢀ
FSYSONꢀbitꢀinꢀCTRLꢀregisterꢀequalꢀtoꢀ“0”.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ
describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:
•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ“HALT”ꢀinstruction,ꢀ
butꢀtheꢀTimeꢀBaseꢀclockꢀandꢀfSUBꢀclockꢀwillꢀbeꢀon
.
•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.
•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀisꢀenabled.ꢀ
•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.
•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀflag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀflag,ꢀTO,ꢀ
willꢀbeꢀcleared.
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�eꢀteꢁꢂeꢃ ꢄꢅꢆ ꢄ01ꢄ
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
