32-Bit ARM® Cortex™-M0+ MCU
HT32F52220/HT32F52230
Reset Control Unit – RSTCU
Supply supervisor:
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● Power On Reset / Power Down Reset – POR/PDR
● Brown-out Detector – BOD
● Programmable Low Voltage Detector – LVD
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
Clock Control Unit – CKCU
External 4 to 16 MHz crystal oscillator
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Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C operating
temperature
Internal 32 kHz RC oscillator
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Integrated system clock PLL
Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a
Low Speed Internal RC oscillator (LSI), a Phase Lock Loop (PLL), a HSE clock monitor, clock
prescalers, clock multiplexers, APB clock divider and gating circuitry. The AHB, APB and
CortexTM-M0+ clocks are derived from the system clock (CK_SYS) which can come from the HSI,
HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use the LSI as their clock source.
Power Management – PWRCU
Single VDD power supply: 2.0 V to 3.6 V
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Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply
Two power domains: VDD, 1.5 V.
Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
Rev. 1.21
8 of 39
April 11, 2017
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
