HT27C040
Test Conditions
Symbol
Parameter
Min.
Typ. Max.
Unit
VCC
Conditions
Programming operation
tAS
Address Setup Time
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
6V
2
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
75
¾
¾
¾
¾
¾
¾
ms
ms
ms
ms
ms
ns
ms
ms
ms
ms
ns
ms
tOES
tDS
OE Setup Time
Data Setup Time
2
¾
tAH
Address Hold Time
0
¾
tDH
Data Hold Time
2
¾
tDFP
tVPS
tPW
tVCS
tCES
tOE
Output Enable to Output Float Delay
VPP Setup Time
0
130
¾
2
CE Program Pulse Width
VCC Setup Time
50
2
105
¾
CE Setup Time
2
¾
Data Valid from OE
150
¾
¾
2
tPRT
VPP Pulse Rise Time During Programming
Test waveforms and measurements
Output test load
2
.
4
V
1
.
3
V
2
.
0
V
A
M
L
C
A
C
D
r
i
v
i
n
g
e
a
s
u
r
e
m
e
n
t
L
e
v
e
l
s
(
1
N
9
1
4
)
e
v
e
l
0
.
8
V
0
.
4
5
V
3
.
3
k
tR, tF< 20ns (10% to 90%)
O
u
t
p
u
t
P
i
n
C
L
Note: CL=100pF including jig capacitance
Functional Description
Programming of the HT27C040
HT27C040. This process is repeated while sequencing
through each address of the HT27C040. This part of
the programming algorithm is done at VCC=6.0V to as-
sure that each EPROM bit is programmed to a suffi-
ciently high threshold voltage. This ensures that all bits
have sufficient margin. After the final address is com-
pleted, the entire EPROM memory is read at
When the HT27C040 is delivered, the chip has all
4096K bits in the ²ONE², or HIGH state. ²ZEROs² are
loaded into the HT27C040 through programming.
The programming mode is entered when 12.5±0.2V is ap-
plied to the VPP pin, OE is at VIH, and CE is VIL. For pro-
gramming, the data to be programmed is applied with 8
bits in parallel to the data pins.
VCC=VPP=5.25±0.25V to verify the entire memory.
Program inhibit mode
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 50ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is veri-
fied or until the maximum number of pulses is reached
while sequencing through each address of the
Programming of multiple HT27C040 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27C040 may be common. A TTL low-level
program pulse applied to an HT27C040 CE input with
VPP=12.5±2V, and OE HIGH will program that
HT27C040. A high-level CE input inhibits the
HT27C040 from being programmed.
Rev. 1.00
4
April 30, 2001
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
