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HT24LC64(8TSSOP-A) 参数 Datasheet PDF下载

HT24LC64(8TSSOP-A)图片预览
型号: HT24LC64(8TSSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器LTE
文件页数/大小: 12 页 / 126 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT24LC64  
The 8th bit device address is the read/write operation  
select bit. A read operation is initiated if this bit is high  
and a write operation is initiated if this bit is low.  
The data word address lower 5 bits are internally in-  
cremented following the receipt of each data word.  
The higher data word address bits are not incre-  
mented, retaining the memory page row location.  
When the word address, internally generated,  
reaches the page boundary, the following byte is  
placed at the beginning of the same page. If more  
than 32 data words are transmitted to the EEPROM,  
the data word address will ²roll over² and previous  
data will be overwritten.  
If the comparison of the device address succeed the  
EEPROM will output a zero at ACK bit. If not, the chip will  
return to a standby state.  
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Device Address  
·
Acknowledge polling  
To maximize bus throughput, one technique is to allow  
the master to poll for an acknowledge signal after the  
start condition and the control byte for a write com-  
mand have been sent. If the device is still busy imple-  
menting its write cycle, then no ACK will be returned.  
The master can send the next read/write command  
when the ACK signal has finally been received.  
Write Operations  
·
Byte write  
A write operation requires two data word address fol-  
lowing the device address word and acknowledgment.  
Upon receipt of this address, the EEPROM will again  
respond with a zero and then clock in the first 8-bit data  
word. After receiving the 8-bit data word, the EEPROM  
will output a zero and the addressing device, such as a  
microcontroller, must terminate the write sequence  
with a stop condition. At this time the EEPROM enters  
an internally-timed write cycle to the nonvolatile mem-  
ory. All inputs are disabled during this write cycle and  
EEPROM will not respond until the write operation is  
completed (refer to Byte write timing).  
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Page write  
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The 64K EEPROM is capable of a 32-byte page write.  
A page write is initiated in the same way as a byte write,  
but the microcontroller does not send a stop condition  
after the first data word is clocked in. Instead, after the  
EEPROM acknowledges the receipt of the first data  
word, the microcontroller can transmit up to 31 more  
data words. The EEPROM will respond with a zero af-  
ter each data word received. The microcontroller must  
terminate the page write sequence with a stop condi-  
tion (refer to Page write timing).  
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Byte Write Timing  
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Page Write Timing  
Rev. 1.40  
4
June 22, 2010