PATENTED
HT1620
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
Setup Time for CS to WR,RD
tSU1
3V
3V
500
50
600
100
ns
ns
¾
¾
¾
Clock Width
(Figure 3)
Hold Time for CS to WR, RD
tH1
tOFF
tSR
¾
Clock Width
(Figure 3)
VDD OFF Times (Figure 4)
VDD Rising Slew Rate (Figure 4)
VDD drop down to 0V
20
ms
¾
¾
¾
¾
¾
¾
0.05
V/ms
¾
Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
V
A
L
I
D
D
A
T
A
V
G
D
D
t
f
t
r
D
B
5
0
%
V
G
D
D
N
W
R
,
R
D
0 %
9
t
s
u
t
h
5
k
1
0
%
C
l
o
c
N
0
%
V
G
D
D
t
C
L
K
t
C
L
K
W
R
,
R
D
5
0
%
C
l
o
c
k
N
Figure 2
Figure 1
t
C
S
V
G
D
D
5
0
%
C
S
N
t
h
1
V
D
D
t
s
u
1
t
S
R
0
V
V
G
D
D
W
R
,
R
D
t
O
F
F
5
0
%
C
l
o
c
k
N
F
I
R
S
T
L
A
S
T
C
l
o
c
k
C
l
o
c
k
Figure 4. Power-on Reset Timing
Figure 3
Rev. 1.80
7
July 27, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
