PATENTED
Pad Assignment
O S C O
D A T A
O S C I
V D D
C C 1
V S S
IR Q
W R
R D
C S
B Z
B Z
HT1620
C C 2
1
V O 1 5 N
V E E
3
C O M 0
C O M 1
C O M 2
5 1
2
4
5
6
7
8
9
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1 4 0
C O
S E
S E
S E
M 3
G 0
G 1
G 2
(0 ,0 )
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G
S E G
S E G
S E G
S E G
S E G
2 6
2 5
2 4
2 3
2 2
2 1
1 0
1 1
1 2
1 3
S E G 3
S E G 4
S E G 5
1 4
S E G 6
1 5
S E G 7
1 6
S E G 8
1 7
S E G 9
1 8 1 9
S E G 1 0
S E G 1 1
2 0
S E G 1 2
2 1 2 2
S E G 1 4
S E G 1 3
2 3 2 4
S E G 1 5
S E G 1 6
2 5 2 6
S E G 1 7
S E G 1 8
2 7
S E G 1 9
S E G 2 0
Chip size: 92
´
89 (mil)
2
Bump height: 18mm
±
3mm
Min. Bump spacing: 23.102mm
Bump size: 76
´
76mm
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.80
3
July 27, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
