HT1621
S E G 1
S E G 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
7
4
5
6
8
9
0
1
0
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
IR Q
B Z
B Z
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
H T 1 6 2 1 B
4 8 L Q F P -A
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S G E
S E G
S E G
S E G
S E G
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
S E
S E
S E
S E
S E
S E
S E
S E
C O
C O
C O
C O
G 2
G 2
G 2
G 2
G 2
G 2
G 3
G 3
M 3
M 2
M 1
M 0
1
0
9
7
8
6
5
4
Pad Assignment
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 8
S E G 9
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
4 8
C S
1
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
R D
W R
D A T A
4
5
6
V S S
O S C O
3
2
3 2
3 1
(0 ,0 )
3 0
2 9
2 8
2 7
2 6
2 5
2 4
7
8
2 3
2 2
2 1
1 1
B Z
1 2
B Z
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
O S C I
V L C D
V D D
9
1 0
IR Q
1 3
C O M 0
1 4
C O M 1
1 5
C O M 2
1 6
C O M 3
1 7
S E G 3 1
1 8
S E G 3 0
1 9
S E G 2 9
2 0
Chip size: 127
´
131 (mil)
2
Bump height: 18mm
±
3mm
Min. Bump spacing: 72.36mm
Bump size: 96.042
´
96.042mm
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.30
3
August 6, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
