HT1621
A.C. Characteristics
Symbol
f
SYS1
f
SYS2
f
SYS3
Parameter
System Clock
System Clock
System Clock
Test Conditions
V
DD
¾
¾
¾
¾
f
LCD
LCD Clock
¾
¾
t
COM
f
CLK1
LCD Common Period
Serial Data Clock (WR pin)
5V
3V
f
CLK2
f
TONE
t
CS
Serial Data Clock (RD pin)
5V
Tone Frequency
Serial Interface Reset Pulse
Width (Figure 3)
¾
¾
3V
t
CLK
WR, RD Input Pulse Width
(Figure 1)
5V
Read mode
t
r
, t
f
t
su
t
h
t
su1
t
h1
Rise/Fall Time Serial Data
Clock Width (Figure 1)
Setup Time for DATA to WR,
RD Clock Width (Figure 2)
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
Setup Time for CS to WR, RD
Clock Width (Figure 3)
Hold Time for CS to WR, RD
Clock Width (Figure 3)
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3.34
¾
¾
¾
¾
¾
Read mode
Write mode
6.67
1.67
On-chip RC oscillator
CS
Write mode
Duty cycle 50%
¾
3V
Duty cycle 50%
4
¾
¾
¾
¾
3.34
Conditions
On-chip RC oscillator
Crystal oscillator
External clock source
On-chip RC oscillator
Crystal oscillator
External clock source
n: Number of COM
Min.
¾
¾
¾
¾
¾
¾
¾
4
Typ.
256
32.768
256
f
SYS1
/1024
f
SYS2
/128
f
SYS3
/1024
n/f
LCD
¾
¾
¾
¾
2.0 or 4.0
250
¾
¾
¾
¾
120
120
120
100
100
Max.
¾
¾
¾
¾
¾
¾
¾
150
300
75
150
¾
¾
125
¾
125
¾
¾
¾
¾
¾
¾
Ta=25°C
Unit
kHz
kHz
kHz
Hz
Hz
Hz
s
kHz
kHz
kHz
kHz
kHz
ns
ms
ms
ns
ns
ns
ns
ns
t
f
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
t
r
V
t
C
L K
D D
V a lid D a ta
D B
V
t
h
U
D D
5 0 %
t
S
t
C
G N D
L K
G N D
V
D D
Figure 1
t
C
S
W R , R D
C lo c k
5 0 %
G N D
Figure 2
V
D D
C S
5 0 %
t
S
U 1
t
h
1
G N D
V
D D
W R , R D
C lo c k
5 0 %
F ir s t C lo c k
L a s t C lo c k
G N D
Figure 3
Rev. 1.70
6
June 29, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
