HT1621
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
2
59.46
22.18
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
58.14
58.14
58.14
58.14
58.14
58.14
58.14
58.14
55.55
48.92
42.29
35.66
29.03
22.40
15.77
9.14
-55.04
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-58.52
-44.07
-31.58
-20.70
-13.98
-7.05
-25.29
-18.66
-11.94
-5.31
1.32
3
15.56
4
5.36
5
-4.51
6
7.95
-11.14
-34.76
-41.90
-49.13
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-59.08
-58.44
-51.81
-45.18
-38.55
-31.92
7
14.58
21.21
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
59.46
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-0.34
6.33
2.42
12.96
-4.21
-10.84
-17.47
-24.10
-30.73
-38.17
-45.39
19.59
58.14
58.14
58.14
58.14
58.14
Pad Description
Pad No.
Pad Name
I/O
Function
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command trans-
mission between the host controller and the HT1621 are all enabled.
1
CS
I
READ clock input with pull-high resistor
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host control-
ler can use the next rising edge to latch the clocked out data.
2
3
RD
I
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
WR
4
5
7
DATA
VSS
I/O Serial data input/output with pull-high resistor
Negative power supply, ground
¾
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
6
OSCO
O
8
VLCD
VDD
I
LCD power input
9
Positive power supply
¾
O
O
O
O
10
IRQ
Time base or WDT overflow flag, NMOS open drain output
2kHz or 4kHz tone frequency output pair
LCD common outputs
11, 12
13~16
48~17
BZ, BZ
COM0~COM3
SEG0~SEG31
LCD segment outputs
Rev. 1.70
4
June 29, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
