HT1620
Functional Description
Display memory
-
RAM structure
The static display RAM is organized into 32´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and READ-MOD
IFY-WRITE commands. The following is a map-
ping from the RAM to the LCD patterns.
C O M 3
S E G 0
S E G 1
S E G 2
S E G 3
3
2
A d d r e s s 6 b its
(A 5 , A 4 , ..., A 0 )
1
C O M 2
C O M 1
C O M 0
0
Buzzer tone output
A simple tone generator is implemented in the
HT1620. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.
LCD driver
The HT1620 is a 128 (32´4) pattern LCD driver.
It can be configured as 1/2 or 1/3 bias and 2 or 3
or 4 commons of LCD driver by the S/W configu-
ration. This feature makes the HT1620 suitable
for multiple LCD applications. The LCD driving
clock is derived from the system clock. The value
of the driving clock is always 256Hz even when it
is at a 32.768kHz crystal oscillator frequency. The
LCD corresponding commands are summarized
in the table.
The bold form of 1 0 0, namely
1 0 0,
indicates
the command mode ID. If successive commands
have been issued, the command mode ID will be
omitted, except for the first command. The LCD
OFF command turns the LCD display off by dis-
abling the LCD bias generator. The LCD ON
command, on the other hand, turns the LCD
display on by enabling the LCD bias generator.
The BIAS and COM are the LCD panel related
commands. With the use of the LCD related
commands, the HT1620 can be compatible with
most types of LCD panels.
S E G 3 1
D
3
D
2
D
1
D
0
3 1
A d d r
D a ta
D a ta 4 b its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
Time base and watchdog timer
-
WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will stay at a logic
low level until the CLR WDT or the IRQ DIS
command is issued.
T im e B a s e
C lo c k S o u r c e
/2 5 6
V D D
C L R
T im e r
W D T
/4
D
C K
R
T IM E R
E N /D IS
IR Q
W D T E N /D IS
Q
IR Q
E N /D IS
C L R
W D T
Timer and WDT configurations
9
July 26, 1999
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
