HT113JA
Pad Assignment
S E G 2 2
S E G 2 0
S E G 3 1
6 5
S E G 3 0
6 4
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 1 9
S E G 1 8
S E G 2 1
V D D
6 6
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
B Z
B Z
V L C D
T 2 5 6
C O M 3
C O M 2
C O M 1
C O M 0
N C
N C
N C
N C
®
¬
S T A R T /P A U S E
M U T E
O N /O F F
N C
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
S E G 1 7
S E G 1 6
S E G 1 5
S E G 1 4
S E G 1 3
S E G 1 2
S E G 1 1
S E G 1 0
S E G 9
S E G 8
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
N C
(0 ,0 )
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
1 4
1 5
1 6
1 7
1 8
2 1
1 9
2 0
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
* The IC substrate should be connected to VSS in the PCB layout artwork.
V S S
O S C I
Chip size: 2780´2990 (mm)
2
O S C O
T 1 D
K E Y 4
K E Y 3
K E Y 2
K E Y 1
¯
B
A
N C
R E S E T
8
December 14, 1999
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
