Preliminary
Pin Assignment
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 4
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 2
P C 0 /T M R
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
P C 0 /T M R
P C 1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2
HT48E30
H T 4 8 E 3 0
2 4 S K D IP -A /S O P -A
H T 4 8 E 3 0
2 8 S K D IP -A /S O P -A
Pad Assignment
P A 2
1
P A 3
3 1
P B 4
3 0
P B 5
2 9
P B 6
2 8
P B 7
2 7
P A 4
2 6
P A 5
2 5
T R IM 1
2
3
4
T R IM 2
T R IM 3
2 4
(0 ,0 )
P A 1
5
6
7
8
9
1 0
1 1
2 0
1 9
1 2
1 3
1 4
1 5
1 6
1 7
1 8
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
2 3
2 2
2 1
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2
P C 1
P G 0 /IN T
* The IC substrate should be connected to VSS in the PCB layout artwork.
P C 0 /T M R
Rev. 0.00
2
January 12, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
