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48E30 参数 Datasheet PDF下载

48E30图片预览
型号: 48E30
PDF下载: 下载PDF文件 查看货源
内容描述: 8位I / O型微控制器(带有EEPROM ) [8-Bit I/O Type MCU (With EEPROM)]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 44 页 / 352 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48E30
Preliminary
Features
·
Operating voltage:
·
HALT function and wake-up feature reduce power
8-Bit I/O Type MCU (With EEPROM)
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
Low voltage reset function
·
23 bidirectional I/O lines (max.)
·
1 interrupt input shared with an I/O line
·
8-bit programmable timer/event counter with overflow
consumption
·
4-level subroutine nesting
·
Up to 0.5ms instruction cycle with 8MHz system clock
at V
DD
=5V
·
Bit manipulation instruction
·
14-bit table read instruction
·
63 powerful instructions
·
10
6
erase/write cycles EEPROM data memory
·
EEPROM data retention > 10 years
·
All instructions in one or two machine cycles
·
In system programming (ISP)
·
24/28-pin SKDIP/SOP package
interrupt and 8-stage prescaler
·
On-chip crystal and RC oscillator
·
Watchdog Timer
·
2048´14 program memory ROM (MTP)
·
128´8 data memory EEPROM
·
96´8 data memory RAM
·
Buzzer driving pair and PFD supported
General Description
The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P G 0
In te rru p t
C ir c u it
S T A C K
4 L e v e ls
T M R 0
IN T C
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
M
U
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
M
U
X
P r e s c a le r
T M R /P C 0
M
U
X
f
S
Y S
P ro g ra m
R O M
P ro g ra m
C o u n te r
E N /D IS
f
S
Y S
/4
M P
W D T O S C
P A C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
M U X
P A
B Z /B Z
P B C
P G 1
P G 2
P B
P C C
O S C 2
O S
R E
V D
V S
C 1
S
D
S
A C C
P C
P O R T C
P O R T B
P B 0 ~ P B 7
P O R T A
P A 0 ~ P A 7
S T A T U S
P C 0 ~ P C 5
D a ta M e m o ry
E E P R O M
E E C R
P G C
P G
P O R T G
P G 0
Rev. 0.00
1
January 12, 2004