HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
A typical READ cycle is shown in Figure 13
In general, in Open Mode the LD_SDO line is always active during the WRITE cycle. During any Open
Mode SPI cycle LD_SDO will contain the data from the current address written in Reg0h[7:3]. If Reg0h[7:3]
is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in
progress.
If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the desired
address to Reg0h[7:3], then in the next SPI cycle the desired data will be available on LD_SDO.
An example of the Open Mode two cycle procedure to read from any random address is as follows:
a. The Master (host), on the first 24 falling edges of SCLK places 24-bit data, d23:d0, MSB first, on SDI
as shown inFirst Cycle Figure 13. d23:d5 should be set to zero. d4:d0 = address of the register to be
READ on second cycle.
b. the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address , r4:r0, (the READ ADDRESS register), MSB first, on the next 5
falling edges of SCLK (25-29). r4:r0=00000.
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32)..Chip
address is always 000 for RF PLL with Integrated VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the the address transfer of the two part READ cycle.
j. If one does not wish to write data to the chip at the same time as we do the second cycle , then it is
recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of
the cycle.
k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCLK.
l. Slave (PLL with Integrated VCO) shifts the SDI data on the next 32 rising edges of SCLK. On these
same edges the Slave places the desired read data (ie. data from the address specified in Reg0h[7:3]
of the first cycle) on LD_SDO which automatically switches to SDO mode from LD mode, disabling
the LD output.
m. Master asserts SEN after the 32nd rising edge of SCLK to complete the cycle and revert back to Lock
Detect on LD_SDO.
Table 7. SPI Open Mode - Read Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max
Units
ns
t
t
t
t
t
SDI setup time to SCLK Rising Edge
SCLK Rising Edge to SDI hold time
SEN low duration
3
1
2
3
4
5
3
ns
10
10
ns
SEN high duration
ns
SCLK Rising Edge to SDO setup time
8.2ns+0.211ns/pF
ns
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Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
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