HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Figure 12. Open Mode - Serial Port Timing Diagram - WRITE
Open Mode - Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 6. SPI Open Mode - WRITE Timing Characteristics
Parameter
Conditions
SDI setup time to SCLK Rising Edge
SCLK Rising Edge to SDI hold time
SEN low duration
Min.
Typ.
Max
Units
ns
t
t
t
t
t
3
1
2
3
4
5
3
ns
10
10
10
ns
SEN high duration
ns
SCLK 32 Rising Edge to SEN Rising Edge
Max Serial port Clock Speed
ns
50
MHz
Open Mode - Serial Port WRITE Operation cont’d
a.
The Master (host) places 24-bit data, d23:d0, MSB first, on SDI on the first 24 falling edges of SCLK.
b. the slave (PLL with Integrated VCO) shifts in data on SDI on the first 24 rising edges of SCLK
c. Master places 5-bit register address to be written to, r4:r0, MSB first, on the next 5 falling edges of SCLK
(25-29)
d. Slave shifts the register bits on the next 5 rising edges of SCLK (25-29).
e. Master places 3-bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (30-32).
Hittite reserves chip address a2:a0 = 000 for all RF PLL with Integrated VCOs.
f. Slave shifts the chip address bits on the next 3 rising edges of SCLK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCLK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the WRITE cycle.
Open Mode - Serial Port READ Operation
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
41
Application Support: Phone: 978-250-3343 or apps@hittite.com
HITTITE [ HITTITE MICROWAVE CORPORATION ]
